Computer System Design Lecture 5

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Presentation transcript:

241-440 Computer System Design Lecture 5 Wannarat Suntiamorntut 241-440 @ W.S.

Part II: Control Path for (Single Cycle) 241-440 @ W.S.

Outline Control for Register-Register Or Immediate Instructions Control Signal for Load/Store Branch Jump Local control : ALU control Main control 241-440 @ W.S.

Single Cycle Datapath 241-440 @ W.S.

Add Instruction Add rd, rs, rt - Mem[PC] - R[rd] <= R[rs] + R[rt] - PC = PC + 4 241-440 @ W.S.

Fetch Unit : Add 241-440 @ W.S.

Single Cycle Datapath : Add 241-440 @ W.S.

Fetch Unit : End of Add 241-440 @ W.S.

Single Cycle Datapath : Immed. 241-440 @ W.S.

Single Cycle Datapath : Immed. 241-440 @ W.S.

Single Cycle Datapath : Load 241-440 @ W.S.

Single Cycle Datapath : Store 241-440 @ W.S.

Single Cycle Datapath : Branch 241-440 @ W.S.

End of Branch instruction 241-440 @ W.S.

Summary of Control Signal 241-440 @ W.S.

Table of summary control signal 241-440 @ W.S.

Concept of Logical Control 241-440 @ W.S.

Decode of “func” Field 241-440 @ W.S.

241-440 @ W.S.

Truth Table for Main Control 241-440 @ W.S.

Put It Together 241-440 @ W.S.

Worst Case timing Load 241-440 @ W.S.

Next on Lecture 6 241-440 @ W.S.