Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/

The npn Gummel-Poon Static Model RC ICC - IEC = IS(exp(vBE/NFVt - exp(vBC/NRVt)/QB B RBB ILC IBR B’ ILE IBF RE E ©rlc L34-27Apr2011

Gummel Poon npn Model Equations IBF = ISexpf(vBE/NFVt)/BF ILE = ISEexpf(vBE/NEVt) IBR = ISexpf(vBC/NRVt)/BR ILC = ISCexpf(vBC/NCVt) QB = (1 + vBC/VAF + vBE/VAR )  {½ + [¼ + (BFIBF/IKF + BRIBR/IKR)]1/2 } ©rlc L34-27Apr2011

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Values for fms with metal gate ©rlc L34-27Apr2011

Values for fms with silicon gate ©rlc L34-27Apr2011

Typical fms values Fig 10.15* fms (V) NB (cm-3) ©rlc L34-27Apr2011

Flat band with oxide charge (approx. scale) SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) q(fm-cox) Ex Eg,ox~8eV EFm Ec EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev ©rlc L34-27Apr2011

Flat-band parameters for n-channel (p-subst) ©rlc L34-27Apr2011

Flat-band parameters for p-channel (n-subst) ©rlc L34-27Apr2011

Inversion for p-Si Vgate>VTh>VFB Vgate> VFB EOx,x> 0 e- e- e- e- e- Depl Reg Acceptors Vsub = 0 ©rlc L34-27Apr2011

Approximation concept “Onset of Strong Inv” OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG = VTh Assume ns = 0 for VG < VTh Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh Cd,min = eSi/xd,max for VG > VTh Assume ns > 0 for VG > VTh ©rlc L34-27Apr2011

MOS Bands at OSI p-substr = n-channel Fig 10.9* 2q|fp| qfp xd,max ©rlc L34-27Apr2011

Computing the D.R. W and Q at O.S.I. Ex Emax x ©rlc L34-27Apr2011

Calculation of the threshold cond, VT ©rlc L34-27Apr2011

Equations for VT calculation ©rlc L34-27Apr2011

Fully biased n-MOS capacitor VG Channel if VG > VT VS VD EOx,x> 0 n+ e- e- e- e- e- e- n+ p-substrate Vsub=VB Depl Reg Acceptors y ©rlc L34-27Apr2011 L

MOS energy bands at Si surface for n-channel Fig 8.10** ©rlc L34-27Apr2011

Computing the D.R. W and Q at O.S.I. Ex Emax x ©rlc L34-27Apr2011

Q’d,max and xd,max for biased MOS capacitor Fig 8.11** xd,max (mm) ©rlc L34-27Apr2011

Fully biased n- channel VT calc ©rlc L34-27Apr2011

n-channel VT for VC = VB = 0 Fig 10.20* ©rlc L34-27Apr2011

References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986 ©rlc L34-27Apr2011