Topics Multipliers.

Elementary school algorithm 0 1 1 0 multiplicand x 1 0 0 1 multiplier 0 1 1 0 + 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 + 0 1 1 0 0 1 1 0 1 1 0 partial product

Word serial multiplier + register

Combinational multiplier Uses n-1 adders, eliminates registers:

Array multiplier Array multiplier is an efficient layout of a combinational multiplier. Array multipliers may be pipelined to decrease clock period at the expense of latency.

Array multiplier organization 0 1 1 0 x 1 0 0 1 + 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1 0 multiplicand multiplier skew array for rectangular layout product

Unsigned array multiplier x2y0 x1y0 x0y0 + x1y1 + x0y1 + x1y2 + x0y2 xn-1yn-1 + + P(2n-1) P0 P(2n-2)

Unsigned array multiplier, cont’d

Array multiplier critical path

Verilog for multiplier row module multrow(part,x,ym,yo,cin,s,cout); /* A row of one-bit multiplies */ input [2:0] part; input [3:0] x; input ym, yo; input [2:0] cin; output [2:0] s; output [2:0] cout; assign {cout[0],s[0]} = part[1] + (x[0] & ym) + cin[0]; assign {cout[1],s[1]} = part[2] + (x[1] & ym) + cin[1]; assign {cout[2],s[2]} = (x[3] & yo) + (x[2] & ym) + cin[2]; endmodule

Verilog for last multiplier row module lastrow(part,cin,s,cout); /* Last row of adders with full carry chain. */ input [2:0] part; input [2:0] cin; output [2:0] s; output cout; wire [1:0] carry; assign {carry[0],s[0]} = part[0] + cin[0]; assign {carry[1],s[1]} = part[1] + cin[1] + carry[0]; assign {cout,s[2]} = part[2] + cin[2] + carry[1]; endmodule

Verilog for multiplier module array_mult(x,y,p); input [3:0] x; input [3:0] y; output [7:0] p; wire [2:0] row0, row1, row2, row3, c0, c1, c2, c3; /* generate first row of products */ assign row0[2] = x[2] & y[0]; assign row0[1] = x[1] & y[0]; assign row0[0] = x[0] & y[0]; assign p[0] = row0[0]; assign c0 = 3’b000; multrow p0(row0,x,y[1],y[0],c0,row1,c1); assign p[1] = row1[0]; multrow p1(row1,x,y[2],y[1],c1,row2,c2); assign p[2] = row2[0]; multrow p2(row2,x,y[3],y[2],c2,row3,c3); assign p[3] = row3[0]; lastrow l({x[3] & y[3],row3[2:1]},c3,p[6:4],p[7]); endmodule

Baugh-Wooley multiplier Algorithm for two’s-complement multiplication. Adjusts partial products to maximize regularity of multiplication array. Moves partial products with negative signs to the last steps; also adds negation of partial products rather than subtracts.

Booth multiplier Encoding scheme to reduce number of stages in multiplication. Performs two bits of multiplication at once—requires half the stages. Each stage is slightly more complex than simple multiplier, but adder/subtracter is almost as small/fast as adder.

Booth encoding Two’s-complement form of multiplier: y = -2nyn + 2n-1yn-2 + 2n-2yn-2 + ... Rewrite using 2a = 2a+1 - 2a: y = -2n(yn-1-yn) + 2n-1(yn-2 -yn-1) + 2n-2(yn-3 -yn-2) + ... Consider first two terms: by looking at three bits of y, we can determine whether to add/subtract x, 2x to partial product.

Booth actions yi yi-1 yi-2 increment 0 0 0 0 0 0 1 x 0 1 0 x 0 1 1 2x 0 0 0 0 0 0 1 x 0 1 0 x 0 1 1 2x 1 0 0 -2x 1 0 1 -x 1 1 0 -x 1 1 1 0

Booth example x = 011001 (2510), y = 101110 (-1810). y1y0y-1 = 100, P1 = P0 - (10  011001) = 11111001110. y3y2y1= 111, P2 = P1 0 = 11111001110. y5y4y3= 101, P3 = P2 - 0110010000 = 11000111110.

Booth structure

Wallace tree Reduces depth of adder chain. Built from carry-save adders: three inputs a, b, c produces two outputs y, z such that y + z = a + b + c Carry-save equations: yi = parity(ai,bi,ci) zi = majority(ai,bi,ci)

Wallace tree structure

Wallace tree operation At each stage, i numbers are combined to form ceil(2i/3) sums. Final adder completes the summation. Wiring is more complex. Can build a Booth-encoded Wallace tree multiplier.

Serial-parallel multiplier Used in serial-arithmetic operations. Multiplicand can be held in place by register. Multiplier is shfited into array.

Serial-parallel multiplier structure