Pipelining Chapter 6

Introduction to Pipelining Pipelining is overlapping of tasks to realize improvement in overall performance Consider 4 sub-tasks making up a major task. Lets consider the example given in your text: wash, dry, iron and fold clothes (W D I F) Now consider n-students want to do this WDIF operation this weekend. WDIFWDIFWDIFWDIF WDIF

Instruction Cycle Fetch: Fetch instruction from memory Read: Read registers while decoding the instructions Execute: Execute the operation or calculate an address Access Memory: Read memory Write: Write result to register Assume each of the above operation takes clock cycle. Assume read and write to register happen in different halves of the cycle. Now we can overlap register read and write.

Pipelining Time between instructions in pipelined = time between instructions in non-pipelined / # pipelined stages We want a balanced set of instructions to realized best performance by pipelining Lets examine the MIPS instruction pipelining page: 373 How do we design instruction set for pipelining? MIPS: instructions of same length Only few instruction formats Memory operands only in load and store Operands must be aligned in the memory

Life is not simple It is full of hazards There are situations in pipelining where the next instruction cannot execute in the following cycle. These are called hazards and there are three different types. Structural hazards: instruction fetch and data access of memory Data hazards: add $s0,$t0,$t1 sub $t2,$s0,$t3 Solution: data forwarding Control hazards: branch…delayed branch, rearranging instructions Lets look at some examples