Memory Management by Segmentation Fig 7.38 Main memory … FFF Segment 5 Gap Segment 1 Physical memory addresses Virtual memory addresses Segment 6 Welcome statements and intro to the speaker will go here Gap Segment 9 Segment 3 000

Review

Virtual Memory

Memory Management System (MMU) The MMU interposed between the CPU and the physical memory. Each memory reference issued by the CPU is translated from the logical address space to physical address space. Since there must be translation for each memory reference, the translation must be performed by hardware because of the speed required.

Memory Management and Address Translation

Memory Management using Segmentation

Continued Although less common than paged virtual memory, memory mangaement by segmentation is still used on some machines. Segmentation allows memory to be divided into parcels, or segments of varying sizes depending upon requirements

CS501 Advanced Computer Architecture Lecture 40 Dr.Noor Muhammad Sheikh

Segmentation Mechanism Fig 7.39 Main memory Gap Segment 5 Segment 1 Segment 6 Segment 9 Segment 3 Offset in segment . Virtual memory address from CPU + Segment base register Bounds error No  Segment limit register

The Intel 8086 Segmentation Scheme Fig 7.40 0000 16-bit logical address 16-bit logical address 0000 V 20-bit logical address

Paging (Fig. 7.41) . Secondary memory Virtual memory Physical memory Page n-1 . Program unit Now we want to focus on what a computer is. The speaker may explain the building blocks in this slide . Page 2 Page 1 Page 0

Virtual Address Translation Fig 7.42 Main memory Physical address Desired word . Virtual address from CPU . Physical page Word Offset in page Page number . Hit. Page in Primary memory Page table . Offset in page table + Miss (page fault). Page in Secondary memory . . Page table base register No  Physical page number or pointer to secondary storage Access- control bits: presence bit, dirty bit, usage bits Bounds error Translate to Disk address . Page table limit register

Multiprogramming Servicing the page fault Save the state of suspended process Handle page fault Resume normal execution

TLB (Fig. 7.43) . . . . Main memory or cache Desired word Virtual address from CPU Physical address . Page number Word Physical page Word Hit. Page in Primary memory Associative lookup of virtual page number in TLB . Y Hit The term “computer architecture” was first used at IBM in 1964 by Amdahl, Blaauw, and Brooks [H&P, 2e]. Their definition of architecture was   .... the structure of a computer that a machine language programmer must understand to write a correct (time independent) program for that machine. By architecture they meant the programmer visible portion of the instruction set. Thus a family of machines of the same architecture should be able to run the same software. This concept is now so common that we take it for granted. The x86 architecture is a well known example. Access- control bits: presence bit, dirty bit, usage bits Physical page number Virtual page number TLB miss. Look for physical page in page table To page table

Page Replacement

Flow Chart (fig. 7.44) CPU Virtual address Cache Secondary memory Main memory Search page table Search cache Search TLB Page fault.Get page from secondary memory Page table hit Y Cache hit TLB hit Y Y Update MM. cache, and page table Miss Miss Miss .... the structure of a computer that a machine language programmer must understand to write a correct (time independent) program for that machine.   By architecture they meant the programmer visible portion of the instruction set. Thus a family of machines of the same architecture should be able to run the same software. This concept is now so common that we take it for granted. The x86 architecture is a well known example. Generte physical address Update cache from MM Generte physical address Update TLB Return value from cahce

DMA DMA Controller Main Memory CPU I/O Device I/O Device I/O Device

Summary

Instruction Cache