6.830 Lecture 13 Two-phase Locking Recap Optimistic Concurrency Control

Basic Two Phase Locking Protocol Before every read, acquire a shared lock Before every write, acquire an exclusive lock (or "upgrade") a shared to an exclusive lock Only release locks after all locks have been acquired Lock point = point when all locks are acquired Transaction can run to completion Will be serialized after any conflicting transactions that already completed, and before any other conflict transaction

Example ( 2 x RX WX RY WY ) T1 T2

Example ( 2 x RX WX RY WY ) T1 T2 Slock X

Example ( 2 x RX WX RY WY ) T1 T2 Slock X Read X

Example ( 2 x RX WX RY WY ) T1 T2 Slock X Read X Xlock X

Example ( 2 x RX WX RY WY ) T1 T2 Slock X Read X Xlock X Write X

Example ( 2 x RX WX RY WY ) T1 T2 Slock X Read X Xlock X Write X Release X? If T1 releases X at this point, T2 could update X and Y before T1, resulting in a non-serial schedule.

Example ( 2 x RX WX RY WY ) T1 T2 Slock X Read X Xlock X Write X Release X? Xlock Y

Example ( 2 x RX WX RY WY ) T1 T2 Slock X Read X Xlock X Write X Release X? Xlock Y Release X

Example ( 2 x RX WX RY WY ) T1 T2 Slock X Read X Xlock X Write X Release X? Xlock Y Release X

Example ( 2 x RX WX RY WY ) T1 T2 Slock X Read X Xlock X Write X Release X? Xlock Y Release X Acq Y?

Example ( 2 x RX WX RY WY ) T1 T2 Slock X Read X Xlock X Write X Release X? Xlock Y Release X Acq Y? (Waits for T1)

Two Problems Cascading Aborts & Unrecoverability Deadlocks

Rigorous Two Phase Locking Protocol Before every read, acquire a shared lock Before every write, acquire an exclusive lock (or "upgrade") a shared to an exclusive lock Release locks only after the transaction commits Ensures recoverability/cascadeless, and that commit order = serialization order

Deadlock Detection & Prevention Detection techniques Look for a cycle in waits-for graph Or use a timeout Once a deadlock is found, kill one of the deadlock transactions Release its locks and “roll back” Why is deadlock avoidance not possible?

Why Does 2PC Work? If T1 never waits for a lock from T2, then either T2 acquired and released all its locks before T1 tried to acquire any conflicting locks, or T1 doesn’t conflict with T2 If T1 waits to get a lock from T2, then either: T2 will acquire all of the conflicting locks before T1, in which case the equivalent serial order will be T2-T1 or T1 and T2 will deadlock, in which case one will abort Proof by contradiction. Suppose T1 could have acquired a conflicting lock before T2, in addition to T2 waiting for T1. Two cases: 1) T1 is still holding that lock, in which case T1 and T2 will deadlock Or 2) T1 must have released that lock already. But that’s not possibly by the definition of 2PC, since T1 can’t release a lock until it has acquired all the locks it needs.

OCC Write twrite(object,value): if n not in write_set: // never written, make copy m = read(object) copies[object] = m write_set = write_set U {object} write(copies[object], value)

OCC Read tread(object): read_set = read_set U {object}; if object in write_set: return read(copies[object]); else: return read(object);

Validation Rules When Tj completes its read phase, require that for all Ti < Tj, one of the following conditions must be true for validation to succeed (Tj to commit): Ti completes its write phase before Tj starts its read phase W(Ti) does not intersect R(Tj), and Ti completes its write phase before Tj starts its write phase. W(Ti) does not intersect R(Tj) or W(Tj), and Ti completes its read phase before Tj completes its read phase. W(Ti) does not intersect R(Tj) or W(Tj), and W(Tj) does not intersect R(Ti) [no conflicts] These rules will ensure serializability, with Tj being ordered after Ti with respect to conflicts

Condition 1 Ti completes its write phase before Tj starts its read phase Read Validate Write Ti Read Validate Write Tj Time Don't overlap at all.

W(Ti) intersects W(Tj), i.e., Tj wrote something Ti wrote, or R(Ti) intersects W(Tj), i.e., Ti read something Tj wrote Condition 2 W(Ti) does not intersect R(Tj), and Ti completes its write phase before Tj starts its write phase. W(Ti) ∩ R(Tj) = { } R(Ti) ∩ W(Tj) ≠ { } W(Ti) ∩ W(Tj) ≠ { } Read Validate Write Ti Read Validate Write Tj Time Tj doesn’t read anything Ti wrote. Anything Tj wrote that Ti also wrote will be installed afterwards. Anything Ti read will not reflect Tjs writes

Condition 3 R(Ti) intersects W(Tj), i.e., Ti read something Tj wrote W(Ti) does not intersect R(Tj) or W(Tj), and Ti completes its read phase before Tj completes its read phase. W(Ti) ∩ R(Tj) = { } R(Ti) ∩ W(Tj) ≠ { } W(Ti) ∩ W(Tj) = { } Read Validate Write Ti Read Validate Write Tj Time Tj doesn’t read or write anything Ti wrote (but Ti may read something Tj writes). Ti definitely won’t see any of Tj’s writes, because it finishes reading before Tj starts validation, so Ti ordered before Tj. Ti will always complete its read phase before Tj b/c timestamps assigned after read phase