Two questions Four registers isn’t a lot. What if we need more storage? Who exactly decides which registers are read and written and which ALU function is executed? D data Write D address A address B address A data B data Register File WR DA AA BA A B ALU F Z N C V FS 1/1/2019 ISA

We can access RAM also Here’s a way to connect RAM into our existing datapath. To write to RAM, we must give an address and a data value. These will come from the registers. We connect A data to the memory’s ADRS input, and B data to the memory’s DATA input. Set MW = 1 to write to the RAM. (It’s called MW to distinguish it from the WR write signal on the register file.) n D data WR Write DA D address Register File AA A address B address BA A data B data RAM ADRS DATA CS WR OUT MW +5V n n A B FS FS 1 V ALU C N Z F n Q D1 D0 S n MD 1/1/2019 ISA

Reading from RAM To read from RAM, A data must supply the address. Set MW = 0 for reading. The incoming data will be sent to the register file for storage. This means that the register file’s D data input could come from either the ALU output or the RAM. A mux MD selects the source for the register file. When MD = 0, the ALU output can be stored in the register file. When MD = 1, the RAM output is sent to the register file instead. n D data WR Write DA D address Register File AA A address B address BA A data B data RAM n ADRS n DATA OUT +5V CS A B MW WR FS FS V ALU C N Z F n Q D1 D0 S n MD 1/1/2019 ISA

Notes about this setup We now have a way to copy data between our register file and the RAM. Notice that there’s no way for the ALU to directly access the memory—RAM contents must go through the register file first. Here the size of the memory is limited by the size of the registers; with n-bit registers, we can only use a 2n x n RAM. For simplicity we’ll assume the RAM is at least as fast as the CPU clock. (This is definitely not the case in real processors these days.) D data Write D address A address B address A data B data Register File WR DA AA BA A B ALU F Z N C V FS n Q D1 D0 S RAM ADRS DATA CS OUT MW +5V MD 1/1/2019 ISA

Memory transfer notation In our transfer language, the contents at random access memory address X are denoted M[X]. For example: The first word in RAM is M[0]. If register R1 contains an address, then M[R1] are the contents of that address. The M[ ] notation is like a pointer dereference operation in C or C++. 1/1/2019 ISA

Example sequence of operations Here is a simple series of register transfer instructions: R3  M[R0] R3  R3 + 1 M[R0]  R3 This just increments the contents at address R0 in RAM. Again, our ALU only operates on registers, so the RAM contents must first be loaded into a register, and then saved back to RAM. R0 is the first register in our register file. We’ll assume it contains a valid memory address. How would these instructions execute in our datapath? 1/1/2019 ISA

R3  M[R0] AA should be set to 00, to read register R0. The value in R0 will be sent to the RAM address input, so M[R0] appears as the RAM output OUT. MD must be 1, so the RAM output goes to the register file. To store something into R3, we’ll need to set DA = 11 and WR = 1. MW should be 0, so nothing is accidentally changed in RAM. Here, we did not use the ALU (FS) or the second register file output (BA). n 1 D data WR Write DA D address 11 Register File AA A address B address BA 00 A data B data RAM n ADRS n DATA OUT +5V CS A B MW WR FS FS V ALU C N Z F n Q D1 D0 S n MD 1 1/1/2019 ISA

R3  R3 + 1 AA = 11, so R3 is read from the register file and sent to the ALU’s A input. FS needs to be 00001 for the operation A + 1. Then, R3 + 1 appears as the ALU output F. If MD is set to 0, this output will go back to the register file. To write to R3, we need to make DA = 11 and WR = 1. Again, MW should be 0 so the RAM isn’t inadvertently changed. We didn’t use BA. n 1 D data WR Write DA D address 11 Register File AA A address B address BA 11 A data B data RAM n ADRS n DATA OUT +5V CS 00001 A B MW WR FS FS V ALU C N Z F n D0 n Q D1 S MD 1/1/2019 ISA

M[R0]  R3 Finally, we want to store the contents of R3 into RAM address R0. Remember the RAM address comes from “A data,” and the contents come from “B data.” So we have to set AA = 00 and BA = 11. This sends R0 to ADRS, and R3 to DATA. MW must be 1 to write to memory. No register updates are needed, so WR should be 0, and MD and DA are unused. We also didn’t use the ALU, so FS was ignored. n D data WR Write DA D address Register File AA A address B address BA 00 11 A data B data RAM n ADRS n DATA OUT +5V CS A B MW WR FS FS 1 V ALU C N Z F n Q D1 D0 S n MD 1/1/2019 ISA

Constant in One last refinement is the addition of a Constant input. The modified datapath is shown on the right, with one extra control signal MB. We’ll see how this is used later. Intuitively, it provides an easy way to initialize a register or memory location with some arbitrary number. D data Write D address A address B address A data B data Register File WR DA AA BA Constant MB S D1 D0 Q RAM ADRS DATA CS WR OUT MW +5V A B ALU F Z N C V FS Q D1 D0 S MD 1/1/2019 ISA

Control units From these examples, you can see that different actions are performed when we provide different inputs for the datapath control signals. The second question we had was “Who exactly decides which registers are read and written and which ALU function is executed?” In real computers, the datapath actions are determined by the program that’s loaded and running. A control unit is responsible for generating the correct control signals for a datapath, based on the program code. We’ll talk about programs and control units next. 1/1/2019 ISA

Instruction set architectures We built a simple, but complete, datapath. The datapath is ultimately controlled by a programmer, so today we’ll look at several aspects of programming in more detail. How programs are executed on processors An introduction to instruction set architectures Example instructions and programs Next, we’ll see how programs are encoded in a processor. Following that, we’ll finish our processor by designing a control unit, which converts our programs into signals for the datapath. 1/1/2019 ISA

Programming and CPUs Programs written in a high-level language like C++ must be compiled to produce an executable program. The result is a CPU-specific machine language program. This can be loaded into memory and executed by the processor. CS231 focuses on stuff below the dotted blue line, but machine language serves as the interface between hardware and software. Datapath High-level program Executable file Control words Compiler Control Unit Hardware Software 1/1/2019 ISA

(Instructions in a RAM) Program (Instructions in a RAM) Control signals Control Unit Datapath Status signals 1/1/2019 ISA

High-level languages High-level languages provide many useful programming constructs. For, while, and do loops If-then-else statements Functions and procedures for code abstraction Variables and arrays for storage Many languages provide safety features as well. Static and dynamic typechecking Garbage collection High-level languages are also relatively portable.Theoretically, you can write one program and compile it on many different processors. It may be hard to understand what’s so “high-level” here, until you compare these languages with... 1/1/2019 ISA

Low-level languages Each CPU has its own low-level instruction set, or machine language, which closely reflects the CPU’s design. Unfortunately, this means instruction sets are not easy for humans to work with! Control flow is limited to “jump” and “branch” instructions, which you must use to make your own loops and conditionals. Support for functions and procedures may be limited. Memory addresses must be explicitly specified. You can’t just declare new variables and use them! Very little error checking is provided. It’s difficult to convert machine language programs to different processors. Later we’ll look at some rough translations from C to machine language. 1/1/2019 ISA

Compiling Processors can’t execute programs written in high-level languages directly, so a special program called a compiler is needed to translate high-level programs into low-level machine code. In the “good” old days, people often wrote machine language programs by hand to make their programs faster, smaller, or both. Now, compilers almost always do a better job than people. Programs are becoming more complex, and it’s hard for humans to write and maintain large, efficient machine language code. CPUs are becoming more complex. It’s difficult to write code that takes full advantage of a processor’s features. Some languages, like Perl or Lisp, are usually interpreted instead of compiled. Programs are translated into an intermediate format. This is a “middle ground” between efficiency and portability. 1/1/2019 ISA

Assembly and machine languages Machine language instructions are sequences of bits in a specific order. To make things simpler, people typically use assembly language. We assign “mnemonic” names to operations and operands. There is (almost) a one-to-one correspondence between these mnemonics and machine instructions, so it is very easy to convert assembly programs to machine language. We’ll use assembly code this today to introduce the basic ideas, and switch to machine language tomorrow. 1/1/2019 ISA

Data manipulation instructions Data manipulation instructions correspond to ALU operations. For example, here is a possible addition instruction, and its equivalent using our register transfer notation: This is similar to a high-level programming statement like R0 = R1 + R2 Here, all of the operands are registers. ADD R0, R1, R2 operation destination sources operands R0  R1 + R2 Register transfer instruction: 1/1/2019 ISA

More data manipulation instructions Here are some other kinds of data manipulation instructions. NOT R0, R1 R0  R1’ ADD R3, R3, #1 R3  R3 + 1 SUB R1, R2, #5 R1  R2 - 5 Some instructions, like the NOT, have only one operand. In addition to register operands, constant operands like 1 and 5 are also possible. Constants are denoted with a hash mark in front. 1/1/2019 ISA

Relation to the datapath These instructions reflect the design of our datapath from last week. There are at most two source operands in each instruction, since our ALU has just two inputs. The two sources can be two registers, or one register and one constant. More complex operations like R0  R1 + R2 - 3 must be broken down into several lower-level instructions. Instructions have just one destination operand, which must be a register. D data Write D address A address B address A data B data Register File WR DA AA BA A B ALU F Z N C V FS S D1 D0 Q Constant MB 1/1/2019 ISA

What about RAM? Recall that our ALU has direct access only to the register file. RAM contents must be copied to the registers before they can be used as ALU operands. Similarly, ALU results must go through the registers before they can be stored into memory. We rely on data movement instructions to transfer data between the RAM and the register file. D data Write D address A address B address A data B data Register File WR DA AA BA Q D1 D0 S RAM ADRS DATA CS OUT MW +5V A B ALU F Z N C V FS MD S D1 D0 Q Constant MB 1/1/2019 ISA

Loading a register from RAM A load instruction copies data from a RAM address to one of the registers. LD R1,(R3) R1  M[R3] Remember in our datapath, the RAM address must come from one of the registers—in the example above, R3. The parentheses help show which register operand holds the memory address. D data WR Write DA D address Register File AA A address B address BA A data B data Constant MB S D1 D0 Q RAM ADRS DATA OUT +5V CS A B ALU F Z N C V FS MW WR Q D1 D0 S MD 1/1/2019 ISA

Storing a register to RAM A store instruction copies data from a register to an address in RAM. ST (R3),R1 M[R3]  R1 One register specifies the RAM address to write to—in the example above, R3. The other operand specifies the actual data to be stored into RAM—R1 above. D data Write D address A address B address A data B data Register File WR DA AA BA Constant MB S D1 D0 Q RAM ADRS DATA CS WR OUT MW +5V A B ALU F Z N C V FS Q D1 D0 S MD 1/1/2019 ISA

Loading a register with a constant With our datapath, it’s also possible to load a constant into the register file: LD R1, #0 R1  0 Our example ALU has a “transfer B” operation (FS=10000) which lets us pass a constant up to the register file. This gives us an easy way to initialize registers. D data WR Write DA D address Register File AA A address B address BA A data B data Constant MB S D1 D0 Q RAM ADRS DATA OUT +5V CS A B ALU F Z N C V FS MW WR Q D1 D0 S MD 1/1/2019 ISA

Storing a constant to RAM And you can store a constant value directly to RAM too: ST (R3), #0 M[R3]  0 This provides an easy way to initialize memory contents. D data Write D address A address B address A data B data Register File WR DA AA BA Constant MB S D1 D0 Q RAM ADRS DATA CS WR OUT MW +5V A B ALU F Z N C V FS Q D1 D0 S MD 1/1/2019 ISA

The # and ( ) are important! We’ve seen several statements containing the # or ( ) symbols. These are ways of specifying different addressing modes. The addressing mode we use determines which data are actually used as operands: The design of our datapath determines which addressing modes we can use. The second example above wouldn’t work in our datapath. Why not? We’ll talk about addressing modes in more detail next week. LD R0, #1000 // R0  1000 LD R0, 1000 // R0  M[1000] LD R3, R0 // R3  R0 LD R3, (R0) // R3  M[R0] 1/1/2019 ISA

A small example Here’s an example register-transfer operation. M[1000]  M[1000] + 1 This is the assembly-language equivalent: An awful lot of assembly instructions are needed! For instance, we have to load the memory address 1000 into a register first, and then use that register to access the RAM. This is due to our relatively simple datapath design, which only allows register and constant operands to the ALU. Later on, mostly in CS232, you’ll see why this can be a good thing. LD R0, #1000 // R0  1000 LD R3, (R0) // R3  M[1000] ADD R3, R3, #1 // R3  R3 + 1 ST (R0), R3 // M[1000]  R3 1/1/2019 ISA

Control flow instructions Programs consist of a lot of sequential instructions, which are meant to be executed one after another. Thus, programs are stored in memory so that: Each program instruction occupies one address. Instructions are stored one after another. A program counter (PC) keeps track of the current instruction address. Ordinarily, the PC just increments after executing each instruction. But sometimes we need to change this normal sequential behavior, with special control flow instructions. 768: LD R0, #1000 // R0  1000 769: LD R3, (R0) // R3  M[1000] 770: ADD R3, R3, #1 // R3  R3 + 1 771: ST (R0), R3 // M[1000]  R3 1/1/2019 ISA

Jumps A jump instruction always changes the value of the PC. The operand specifies exactly how to change the PC. For simplicity, we often use labels to denote actual addresses. For example, a program can skip certain instructions. You can also use jumps to repeat instructions. LD R1, #10 LD R2, #3 JMP L K LD R1, #20 // These two instructions LD R2, #4 // would be skipped L ADD R3, R3, R2 ST (R1), R3 LD R1, #0 F ADD R1, R1, #1 JMP F // An infinite loop! 1/1/2019 ISA

Branches A branch instruction may change the PC, depending on whether a given condition is true. LD R1, #10 LD R2, #3 BZ R4, L // Jump to L if R4 == 0 K LD R1, #20 // These instructions may be LD R2, #4 // skipped, depending on R4 L ADD R3, R3, R2 ST (R1), R3 1/1/2019 ISA

Types of branches Branch conditions are often based on the ALU result. This is what the ALU status bits V, C, N and Z are used for. With them we can implement various branch instructions like the ones below. Other branch conditions (e.g., branch if greater, equal or less) can be derived from these, along with the right ALU operation. 1/1/2019 ISA

High-level control flow These jumps and branches are much simpler than the control flow constructs provided by high-level languages. Conditional statements execute only if some Boolean value is true. Loops cause some statements to be executed many times // Find the absolute value of *X R1 = *X; if (R1 < 0) R1 = -R1; // This might not be executed R3 = R1 + R1; // Sum the integers from 1 to 5 R1 = 0; for (R2 = 1; R2 <= 5; R2++) R1 = R1 + R2; // This is executed five times R3 = R1 + R1; 1/1/2019 ISA

Translating the C if-then statement We can use branch instructions to translate high-level conditional statements into assembly code. Sometimes it’s easier to invert the original condition. Here, we effectively changed the R1 < 0 test into R1 >= 0. R1 = *X; if (R1 < 0) R1 = -R1; R3 = R1 + R1; LD R1, (X) // R1 = *X BNN R1, L // Skip MUL if R1 is not negative MUL R1, R1, #-1 // R1 = -R1 L ADD R3, R1, R1 // R3 = R1 + R1 1/1/2019 ISA

Translating the C for loop Here is a translation of the for loop, using a hypothetical BGT branch. R1 = 0; for (R2 = 1; R2 <= 5; R2++) R1 = R1 + R2; R3 = R1 + R1; LD R1, #0 // R1 = 0 LD R2, #1 // R2 = 1 FOR BGT R2, #5, L // Stop when R2 > 5 ADD R1, R1, R2 // R1 = R1 + R2 ADD R2, R2, #1 // R2++ JMP FOR // Go back to the loop test L ADD R3, R1, R1 // R3 = R1 + R1 1/1/2019 ISA

Summary Machine language is the interface between software and processors. High-level programs must be translated into machine language before they can be run. There are three main categories of instructions. Data manipulation operations, such as adding or shifting Data transfer operations to copy data between registers and RAM Control flow instructions to change the execution order Instruction set architectures depend highly on the host CPU’s design. Today we saw instructions that would be appropriate for our datapath from last week. On Wednesday we’ll look at some other possibilities. 1/1/2019 ISA