Day 25: November 7, 2011 Registers ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 25: November 7, 2011 Registers Penn ESE370 Fall2011 -- Mehta & DeHon

Previously… Clocking Discipline Follow discipline of combinational logic broken by registers Compute From state elements Through combinational logic To new values for state elements As long as clock cycle long enough, Will get correct behavior Penn ESE370 Fall2011 -- Mehta & DeHon

Today Clocking: Register Designs Dynamic Static Penn ESE370 Fall2011 -- Mehta & DeHon

Gate-Latch-Register Transistor Count? Total Transistor Width? Capacitive load on data input? Capacitive load on clock? Penn ESE370 Fall2011 -- Mehta & DeHon

Alternate Registers Penn ESE370 Fall2011 -- Mehta & DeHon

How does this work as a register? Penn ESE370 Fall2011 -- Mehta & DeHon

Compare Gate-Latch-Register Transistor Count? Total Transistor Width? Load on input? Load on Clock(s)? Penn ESE370 Fall2011 -- Mehta & DeHon

Weaknesses? Penn ESE370 Fall2011 -- Mehta & DeHon

Weaknesses Hold value on capacitance (“Dynamic”) Not drive to rail Not actively driven Easily upset by noise Will leak away eventually Sets lower bound on clock frequency Cannot “gate off” clock when not in use Not drive to rail Less noise margin More static leakage – PMOS not completely off In 2010: Had good discussion on how long before leak away. Talked about quantifying magnitude… Penn ESE370 Fall2011 -- Mehta & DeHon

How Improve? Remember weaknesses: Holds value dynamically Not driven to rail Penn ESE370 Fall2011 -- Mehta & DeHon

What is the difference? Penn ESE370 Fall2011 -- Mehta & DeHon

Transmission Gates Idea: use both NMOS/PMOS in parallel NMOS passes the strong 0 PMOS passes the strong 1 Pass gates that swing full rail Often used in mux Penn ESE370 Fall2011 -- Mehta & DeHon

Transmission Gate Mux How is this different from a static mux? S S 1 In1 In2 /S 2 /S S How is this different from a static mux? Penn ESE370 Fall2011 -- Mehta & DeHon

How Improve? Remember weaknesses: Holds value dynamically Not driven to rail Penn ESE370 Fall2011 -- Mehta & DeHon

Level Restorer (“Staticizer”) Penn ESE370 Fall2010 -- DeHon

Without level restorer This is just here to show contrast. Penn ESE370 Fall2010 -- DeHon

With level restorer Penn ESE370 Fall2010 -- DeHon

Level Restore What issue arises here? Penn ESE370 Fall2010 -- DeHon

Level Restore What issue arises here? Penn ESE370 Fall2010 -- DeHon 2010: it was tricky to get them to see the ratioed logic here. Penn ESE370 Fall2010 -- DeHon

Register with Level Restore Penn ESE370 Fall2011 -- Mehta & DeHon

Static Register Penn ESE370 Fall2011 -- Mehta & DeHon

Static Register Transistors? Total width? Clock load? Input load? Penn ESE370 Fall2011 -- Mehta & DeHon

Comparison Gate Latch Dynamic Latch Static Latch Area Large Small Moderate Input Cap Delay Slow Fast Dynamic No Yes Full Rail Penn ESE370 Fall2011 -- Mehta & DeHon

Typical Static Register Advantages: Static Full Rail Fast Phi0 Isolation inverters: Input Cap Input/Output Noise State Node Noise /Phi0 Penn ESE370 Fall2011 -- Mehta & DeHon

Admin Midterm Review tonight at 8pm (Moore 204) Tuesday: Andre away (no office hour) Wednesday: Midterm No lecture Midterm 7-9pm in Towne 303 New Project out Thursday: <nothing> (read project) Friday: Class (Andre) Penn ESE370 Fall2011 -- Mehta & DeHon

Ideas Registers can be implemented more compactly with pass transistor-based designs Penn ESE370 Fall2011 -- Mehta & DeHon