Instructor: Dr. Phillip Jones CPRE 583 Reconfigurable Computing Lecture 4: Wed 10/9/2009 (Reconfigurable Computing Systems) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ee.iastate.edu/cpre583/

Overview Cover most of Chapter 3

What you should learn Basic history and some applications of Reconfigurable Computing Systems

Reconfigurable Computing System (RCS) Examples of Characteristics Composed of reconfigurable devices Devices are reprogrammed Give hardware-level of performance Give orders of Magnitude speed up over standard CPUs Can perform a range of applications Spatially Reprogrammed (Heterogeneous Computing) Great talk about the benefits of Heterogeneous Computing http://video.google.com/videoplay?docid=-4969729965240981475# SIMD (Single Instruction Multiple Data) not a RCS A key difference typical all units are homogenous, and follow instructions from a central issuing unit

Early Systems 1960’s: Fixed-Plus-Variable (F+V) University of California Los Angeles (UCLA) “Reconfigurable Computer Origins: The UCLA Fixed-Plus-Variable (F+V) Structure Computer”, 2002, IEEE Annals of the History of Computing. 1980’s: (low logic density devices) Xilinx, Altera, Atmel, Actel FPGA devices used as interface glue logic 10K gates only!! Host Processor + Multiple FPGAs Programmable Active Memories (PAM): 25 FPGAs Virtual Computer Corporation (VCC): ~48 FPGAs Splash: ~32 FPGAs (Cryptology, Pattern Matching)

More Modern Systems 1990’s: Increasing logic densities PRISM: Brown University One of the first uses of a FPGA as a true coprocessor / off loading functional unit CAL (Configurable Logic Array) and XC6200 CAL developed by Algotronix XC6200 developed by Xilinx based off CAL after acquiring Algotronix Dynamic (run-time) Partial Reconfiguration!!!

Circuit Emulation The use of FPGAs to emulate ASICs (Application Specific Integrated Circuits), e.g. Xeon/Optiron Processors. Example platforms PiE QuickTurn InCA Why Bugs in a large processor is expensive!!! Simulation slow (days -> weeks to run 1 ms) Early testing of SW (e.g. boot Windows in one day)

Circuit Emulation Virtual Wires (Work at M.I.T)

Accelerating Technology (Mid-Late 1990’s) FPGAs more generally used, Why? Increased logic density (single device systems) Increasing the performance of standard CPUs becoming more difficult. Memory Bandwidth issues Power/Thermal issues Adaptive Computing Systems (ACS) ~$100 million invested by the department of defense for research over a 5 year period Perhaps motivated England and Japan to push research

Accelerating Technology (Mid-Late 1990’s) New trends Single FPGA devices on standard interface boards (e.g. PCI) Many low coast platforms emerged (10’ -100’s) Issue: No standard tools for programming SW/HW codesign not cleanly supported Tool chain for developing HW (from vendor) Tool chain for developing SW (more standard, e.g. gcc) No clean way to bring the HW and SW design process together Still an on going open research issue today

Reconfigurable Supercomputing (2000’s) A typical architecture composed of many commercial CPU each paired with a large FPGA Produced by major supercomputing players Cray: 100’s of processing nodes (XD1) SRC: Silicon Graphics: Reconfigurable Application Specific Processor (RASP) Newer supercomputing players: Motherboard FPGA/CPU (Personal Supercomputers) XtremeData Nallatec DRC

Slides in Progress Need to revise this lecture with figures, and useful animations Add some non-FPGA systems, maybe not since GARP, and PipeRench were discussed in last lecture. Perhaps just mention again Main reason other archs are not used is economy of scales. Lots of FPGAs are manufacture, thus lowing cost and enable the use of state of the art fab technology (given high performance