CS 140L Lecture 6 Professor CK Cheng 5/05/02.

Slides:

Advertisements

Similar presentations

Lab 2: Finite State Machines CS 3410 Spring 2015.

Advertisements

CS 140 Lecture 16 System Designs Professor CK Cheng CSE Dept. UC San Diego 1.

Lecture 15 Finite State Machine Implementation

Lecture #24 Page 1 EE 367 – Logic Design Lecture #24 Agenda 1.State Machines Review Announcements 1.n/a.

Sequential Circuits Storage elements

State-machine structure (Mealy)

1 CS 140L Lecture 8 System Design Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 10 Sequential Networks: Implementation Professor CK Cheng CSE Dept. UC San Diego 1.

Analysis of Clocked Sequential Circuits

CS 151 Digital Systems Design Lecture 21 Analyzing Sequential Circuits.

CS 151 Digital Systems Design Lecture 37 Register Transfer Level

CS 151 Digital Systems Design Lecture 25 State Reduction and Assignment.

CS 140 Lecture 17 Professor CK Cheng 11/26/02. System Designs 1.Intro 2.Spec 3.Implementation.

CS 140 Lecture 7 Professor CK Cheng 4/23/02. Part II. Sequential Network (Ch ) 1.Flip-flops SR, D, T, JK, 2.SpecificationState Table 3.Implementation.

CS 140 Lecture 9 Professor CK Cheng 4/30/02. Part II. Sequential Network 1.Memory 2.Specification 3.Implementation S XY s i t+1 = g i (S t, x t )

6/12/20151 Sequence Detectors Lecture Notes – Lab 4 Sequence detection is the act of recognizing a predefined series of inputs A sequence detector is a.

CS 140 Lecture 8 Professor CK Cheng 4/26/02. Part II. Sequential Network 1.Memory SR, D, T, JK, 2.Specification S XY s i t+1 = g i (S t, X t )

CSE 140 Lecture 8 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego 1.

1 CS 140 Lecture 9 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 8 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 18 Professor CK Cheng 6/04/02. Part IV. System Designs Algorithm: { Input X, Y type bit-vector, start type boolean; Local-Object A, B type.

Give qualifications of instructors: DAP

CS 140 Lecture 10 Professor CK Cheng 5/02/02. Given the state table, implement with 2 JK flip flops id Q 1 (t) 0 1 Q 0 (t) X(t)

Spring 2002EECS150 - Lec15-seq2 Page 1 EECS150 - Digital Design Lecture 15 - Sequential Circuits II (Finite State Machines revisited) March 14, 2002 John.

CS 140L Lecture 7 Professor CK Cheng 11/12/02. Transformation between Mealy and Moore Machines Algorithm: 1) For each NS, z = S i, j create a state S.

CS 140L Lecture 9 Professor CK Cheng 6/03/02. transistors modules sequential machine system 1.Adders, Muxes 2.F-Fs and counters 3.Finite State Machine.

CS 140 Lecture 11 Professor CK Cheng 5/31/02. C1C2 CLK x(t) y(t) Sequential Network Implementation Mealy & Moore machine State Table  Netlist s(t) D(t)

CS 140 Lecture 10 Professor CK Cheng 10/29/02. Part II. Sequential NetworkReminder 1.Flip flops 2.Specification 3.Implement Netlist  State Table  State.

ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)

CS 140 Lecture 8 Professor CK Cheng 10/22/02. Part II. Sequential Network 1.Flip-flops SR, D, T, JK, State Table Characteristic Eq. Q(t+1) = f(x(t), Q(t)).

ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)

CS 140L Lecture 7 Transformation between Mealy and Moore Machines Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 9 Professor CK Cheng 10/24/02. Sequential Network 1.Components F-Fs 2.Specification D Q Q’ CLK.

CS 151 Digital Systems Design Lecture 31 Read Only Memory (ROM)

CS 140L Lecture 4 Professor CK Cheng 10/22/02. 1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)

Introduction to Sequential Design. Types of Logic Circuits  Logic circuits can be: Combinational Logic Circuits-outputs depend only on current inputs.

FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #8: Introduction to Sequential Logic.

ECE/CS 352 Digital System Fundamentals© T. Kaminski & C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 4 – Part 3 Tom Kaminski & Charles.

L16 – Testbenches for state machines. VHDL Language Elements  More examples HDL coding of class examples Testbench for example  Testing of examples.

VHDL Project I: Introduction to Testbench Design Matthew Murach Slides Available at:

Lecture 18 More Moore/Mealy machines.

Sequential Circuit: Analysis BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.

Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.

CEC 220 Digital Circuit Design Timing Analysis of State Machines

Controllers ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering Dr. Filip Cuckov.

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.

CSE 140: Components and Design Techniques for Digital Systems Lecture 9: Sequential Networks: Implementation CK Cheng Dept. of Computer Science and Engineering.

Dr. ClincyLecture Slide 1 CS Chapter 3 (3A and ) Part 8 of 8 Dr. Clincy Professor of CS.

CSE 140 Lecture 8 Sequential Networks

Sequential Networks and Finite State Machines

Sequential logic design principles

Digital Design Lecture 9

Dr. Clincy Professor of CS

Sequential Networks and Finite State Machines

Algorithmic State Machine (ASM) Charts: VHDL Code & Timing Diagrams

ECE 3130 – Digital Electronics and Design

Finite State Machines Experiment 4 Introduction

EEL 3705 / 3705L Digital Logic Design

CSE 140 Lecture 10 Sequential Networks: Implementation

CSE 140: Components and Design Techniques for Digital Systems

CSE 370 – Winter Sequential Logic-2 - 1

CSE322 Mealy and Moore Machine

CS 140 Lecture 16 Professor CK Cheng 11/21/02.

D Flip-Flop Schematic Block Symbol Truth Table D Q Clk Q Clk D Q(t+1)

Dr. Clincy Professor of CS

SYEN 3330 Digital Systems Chapter 6 – Part 3 SYEN 3330 Digital Systems.

CSE 140 Lecture 9 Sequential Networks

CS 140L Lecture 7 Transformation between Mealy and Moore Machines

CS 140L Lecture 8 Professor CK Cheng 11/19/02.

CS 140L Lecture 6 Professor CK Cheng 11/05/02.

Presentation transcript:

CS 140L Lecture 6 Professor CK Cheng 5/05/02

Lab 3 Finite State Machine Use State Diagram, ABEL layout (VHDL) Mealy, Moore Machines State Assignment Project Manager. New project: Family Spartan, Device S05PC84, Speed 4. State Diagram (ABEL). Create Macro Component. Schematic Diagram: Call the component (Either on top or bottom of list). Synthesis. CLK rst Z x 7. Timing Diagram. 8. Check Layout # CLBs CLB

Transformation between Mealy and Moore Machines Algorithm: Given a state table with entries of NS, z 1) For each NS, z = Si,j create a state Si(j) 2) Replace NS, z (Si ,j) with state Si(j) 3) Set z = j if PS = Si(j)

Example Mealy Machine: Moore Machine: PS A B 00 A,0 A,1 01 A,1 B,0 10 11 (x,y) B,0 B,1 (NS, z) Moore Machine: PS A0 A1 B0 B1 (x,y) 00 A0 A1 01 A1 B0 10 A1 B0 11 B0 B1 z 1

Mealy State Diagram 00/0, 01/1, 10/1 10/0, 01/0, 11/1 11/0 B A 00/1

Moore State Diagram A0 A0 A0 A0 10 00 01 11 11 01 10 10 00 01 00 11 00

Timing Diagrams Time step x y S z A A0 1 A A0 2 1 A A1 3 1 B B0 4 1 B A A0 1 A A0 2 1 A A1 3 1 B B0 4 1 B B1 5 B 1 B0 6 1 A A1 7 B A 1 B0 A1 0 1 Mealy Moore (The output has a 1 clock shift between Mealy and Moore machines)