Chapter 1_5 register Cell Design

Labs Lab 5 Preview on Friday. This Week Lab 4: Up_Down Counter Next Week Lab 5: Serial Multiplier Part 1 Lab 5 Preview on Friday. Bring the lab sheet and preview slides along with you. Make sure you come !!!

Sequential Circuit Design Has been covered in both class and lab. Useful “forever” ….

Overview Part 1 - Registers, Microoperations and Implementations Registers and load enable Register transfer operations Microoperations - arithmetic, logic, and shift Microoperations on a single register Multiplexer-based transfers Shift registers Part 2 - Counters, register cells, buses, & serial operations Microoperations on single register (continued) Counters Register cell design Multiplexer and bus-based transfers for multiple registers Serial transfers and microoperations

Assignment Folder Contents Chapter 10: Questions 3 to 35

rEgIStERs… What are they?

Recap … Registers – used for storing & manipulating data. Register = Daftar Shift Register = Daftar Anjakan Loading (Pembebanan) – is the transfer of information into a register. Load = Beban

Shift Registers …? A register capable of shifting its stored data, in both directions. Consists of a chain of FFs in cascade. The output of one FF goes into the input of the next FF. The shift from one stage to the next is dependent on a common clock pulse.

A 4-Bit Shift Register … Serial output So

… 4-bit Shift Register SI, serial input, is the input to the leftmost FF during the shift. SO, serial output, is taken from the rightmost FF.

Multiplexer-Based Transfers K1:R0 R1, K1K2:R0 R2 Analyse the diagram for input: R2 R1 R0 K2 K1 1 S MUX n=4 Load K1 K2 Load R0 content n.c 1 R2 R1

Multiplexer Approach for Single Register Uses an n-input multiplexer with a variety of transfer sources and functions

REGISTER CELL DESIGN Pages ___ ?

What is a Register Cell? It is a two-state sequential circuit that has: A single- bit cell of an iterative (cascaded) combinational circuit connected to a flip-flop that provides the output

How to design an N-bit Register Cell? Solution: Design a 1-bit register cell with all the associated microoperations, and cascade them to form an n-bit register. Required: An n-bit register cell with one or more associated microoperations.

To be Considered… Is the output of the FF an input to iterative cells? Is the next state dependent on : Its inputs only? Design iterative combinational circuit Attach the iterative circuit to FF Its present state & inputs? May apply sequential design methods

Register Cell Design Assume that a register consists of identical cells Then register design can be approached as follows : Design representative cell for the register Connect copies of the cell together to form the register Register cell design is the first step of the above process

What is Needed? A register Data inputs to the register Control input combinations to the register Example 1 : Not encoded Control inputs : Load, Shift, Add At most, one of Load, Shift, Add is 1 for any clock cycle ( 0, 0, 0 ), ( 1, 0, 0 ), ( 0, 1, 0 ), ( 0, 0, 1 ) Example 2 : Encoded Control inputs : S1, S0 All possible binary combinations on S1, S0 ( 0, 0 ), ( 0, 1 ), ( 1, 0 ), ( 1, 1 )

What else is Needed? A set of register functions ( typically specified as register transfers ) E.g : Load : A  B Shift : A  sr B Add : A  A + B A hold state specification Control inputs : Load, Shift, Add If all control inputs are 0, hold the current register state

Example 7-1

Specs Given Register transfers of register A : Assume that: Only 1 of the operations ( AND, EXOR, OR ) is equal to 1, and For all of the operations ( AND, EXOR, OR ) equal to 0, content of A remains unchanged.

Solution Method 1 Use a register with parallel load constructed from D flip – flop with EN = Load. Combinational circuit needed: Load = OR of all control signals Di = OR of the AND of each control signal with RHS operation How many equations do we need? Something like in Fig. 7.2

Control input combinations to the register … Only 1 of the operations ( AND, EXOR, OR ) is equal to 1 Load = OR of all control signals

… Control input combinations to the register For all of the operations ( AND, EXOR, OR ) equal to 0, content of A (Di)remains unchanged. Di = OR of the AND of each control signal with the RHS operation

… Control input combinations to the register A multiplexer circuit for each D flip-flop

Sketch the Register Cell Design we have just gone through… Hint… Start with the block diagram Then, the complete schematic diagram

WELL Done !!! ….That was for a 1-bit Register Cell Design… Now… what if you were to come up next with a …. 4-bit register cell? 8-bit register cell? Sketch the block diagrams for both

Solution Method 2 If the next state is dependent on the present state & inputs: May apply sequential design methods Design directly for D flip-flops using sequential approach

Remember? Start with the State Table

Then … The K-maps The Flip-flop Equations The Schematic Diagram

Example 1 Again State Table: Four variables give a total of 16 state table entries By using: Combinations of variable names and values Don’t care conditions (for CX = CY = 1) only 8 entries are required to represent the 16 entries Hold Ai v Bi Ai + Bi Ai CX = 0 CY = 0 CX = 1 Bi = 0 Bi = 1 CY = 1 1

Example 1 Again (continued) K-map - Use variable ordering CX, CY, Ai Bi and assume a D flip-flop 1 CY CX Ai X Bi Di

Example 1 Again (continued) The resulting SOP equation: Di = CX Bi + CY Ai Bi + Ai Bi + CY Ai Using factoring and DeMorgan’s law: Di = CX Bi + Ai (CY Bi) + Ai(CY Bi ) Di = CX Bi + Ai + (CY Bi) The gate input cost per cell = 2 + 8 + 2 + 2 = 14 The gate input cost per cell for the previous version is: Per cell: 19 Shared decoder logic: 8 Cost gain by sequential design > 5 per cell Also, no Enable on the flip-flop makes it cost less

Sample Answer to the Register Cell Design Problem

Example 7-2 Please go through… Sketch the schematic diagrams using the first solution method: Using register with parallel load

Exercise 1 A register cell is to be designed for an 8 – bit register A that has the following register transfer functions : Find the logic using AND, OR, and NOT gates for the D input to the D flip – flop in the cell.

Assignment

Multiplexer and Bus-Based Transfers for Multiple Registers

Some Review Slides (from section 7-6) Firstly … Some Review Slides (from section 7-6)

Multiplexer-Based Transfers Multiple inputs are selected by a multiplexer dedicated to the register.

Multiplexer-Based Transfers A Register receives data transfers from more than 1 source. A dedicated multiplexer is used to select the wanted input Example shows: R0 receives data from R2 if K1 is 0. R0 receives data from R1 if K1 is 1. K2 K1 R2 n=4 S R0 1 n=4 R1 MUX n=4

Multiplexer-Based Transfers How do we represent this in RTL form? Written in if-then-else: If (K1=1) then (R0 R1) else if (K2=1) then (R0 R2) Written in RTL K1:R0 R1, K1K2:R0 R2 K2 K1 R2 n=4 S R0 1 n=4 R1 MUX n=4

Multiplexer-Based Transfers K1:R0 R1, K1K2:R0 R2 Analyse the diagram for input: R2 R1 R0 K2 K1 1 S MUX n=4 Load K1 K2 Load R0 content n.c 1 R2 R1

Transforming a Block Diagram into Detailed Logic 1 S MUX n=4 Load Block Diagram Transforming a Block Diagram into Detailed Logic Q0 Q1 Q2 Q3 D0 D1 D2 D3 Load 2 to 1 MUX Y0 Y1 Y2 Y3 A0 A1 A2 A3 B0 B1 B2 B3 S CLK K2 K1 R1 R0 R2 Detailed Logic

Multiplexer and Bus-Based Transfers for Multiple Registers … lets begin

Multiplexer Approach for Single Register Uses an n-input multiplexer with a variety of transfer sources and functions

For more than one Register? 1 Register ≡ 1 Mux? Becomes too large a circuit if there are many registers. Solution 1 Mux for many registers. Use Bus lines.

Dedicated MUX vs Single Mux

Dedicated MUX for Multiple Registers Transfer

Advantages A multiplexer connected to each register input produces a very flexible structure. Characterize the simultaneous transfers possible with this structure.

Limitations A multiplexer is dedicated to each register. Excessive amount of logic. High number of interconnections. Three “n-bit 2-to-1” MUX Each with own “Select” signal. Each register has own “Load” signal.

To overcome the limitations Solution to the problem, use : Shared transfer paths for registers. A shared transfer object is called a bus. Bus implementation using : Multiplexers. Three–state nodes and drivers. In most cases, the number of bits is the length of the receiving register.

Single MUX Bus for Multiple Registers Transfer

Mux Bus - Structure Only need a single n-bit 3-to1-bit MUX and parallel load registers. MUX outputs are shared as a common path (bus). SELECT Determines the contents of the source register. LOAD Determines the destination register, i.e. the register to be loaded with the bus data.

Mux Bus - Limitations 3rd transfer (2 simultaneous transfers): cannot be done Requires 2 simultaneous sources in a single bus. Cannot occur in 1 clock cycle. Requires at least 2 buses. However, dedicated MUX can do this!

Mux Bus – Hardware Reduction A single bus driven by a MUX lowers cost, but limits the available transfers. Characterize the cost savings compared to dedicated MUX…

Dedicated MUX vs MUX Bus

MUX-based vs Bus-based Any combination of transfers is possible. Bus-based Reduction in hardware. Limitation in simultaneous transfers. Simultaneous transfers from different sources in a single clock cycle is impossible.

Three-State (Tri-state) Bus

What is a tri-state buffer? Before that… What is a tri-state buffer?

The Tri-State Buffer Symbol Truth Table IN EN OUT EN IN OUT X Hi-Z 1 For the symbol and truth table, IN is the data input, and EN, the control input. For EN = 0, regardless of the value on IN (denoted by X), the output value is Hi-Z. For EN = 1, the output value follows the input value. Variations: Data input, IN, can be inverted Control input, EN, can be inverted by addition of “bubbles” to signals. IN EN OUT Truth Table EN IN OUT X Hi-Z 1

MUX Bus vs Tri–state Bus

Tri–state Bus: Hardware Reduction The 3–input MUX can be replaced by a tri-state node (bus) and tri-state buffers. Cost is further reduced. Signals can travel in 2 directions. Use the same bus to carry signals into and out of registers.

Question Time … Name the 3 types of alternatives we have discussed. What are they used for? Which one is the best? Why?

Serial Transfers & Microoperations Pages ____

Serial Transfers & Microoperations Used for “narrow” transfer paths Example : Telephone or cable line Parallel – to – Serial : at source Serial – to – Parallel : at destination Serial micro-operations Example 1 : Addition Example 2 : Error – Correction for CDs Parallel  Serial Serial  Parallel Source Destination

Serial Transfers Serial mode  info is transferred / manipulated one bit at a time. Serial transfer from RA to RB is done with shift registers. Serial Transfer of data from Reg. A to Reg. B

Serial Transfers Serial output (SO) of A connected with serial input (SI) of B. SI of A receives 0’s. Data from A transferred to B. Initial content of B shifted out to SO of B and is lost.

Lab 5 – Shift Register in Serial Multiplier MI[3..0] IN[4..0]

Serial Transfers To maintain the data in A, connect SO of A to its SI.

Serial Transfers Shift  determines when & how many times the registers are shifted. Clock pulse (Clock) can pass to C only when Shift is HIGH (1).

Serial Transfers

Serial Micro-operations By using two shift registers for operands, a full adder, and a flip flop (for the carry), we can add two numbers serially, starting at the least significant bit. Serial addition is a low cost way to add large numbers of operands, since a “tree” of full adder cells can be made to any depth. Other operations can be performed serially as well, such as parity generation / checking or more complex error – check codes. Shifting a binary number left = multiplying by 2 E.g sl 0100  1000 Shifting a binary number right = dividing by 2 E.g sr 0100  0010

Serial Adder The circuit shown uses: 2 shift registers for operands, A (3:0) and B (3:0). A full adder, and one more FF (for carry) is used to compute the sum. Results is stored in A register and the final carry in the FF.

Serial Adder SI of B can receive new inputs. Analyze!! SI of B can receive new inputs. In each clock pulse / cycle : New sum bit is transferred to A New carry transferred to FF. Both registers shifted once to the right. Process continues until Shift = 0. 4-bits x 4-bits addition.

Serial Adder What are the pros and cons?

Analyzing the circuit : Serial Adder B3 B2 B1 B0 SUM (A+B) + Cin Cout Cin T0 1 T1 T2 T3 T4 Example 1: Reg A : 1000 Reg B : 0101

Analyzing the circuit : Serial Adder B3 B2 B1 B0 SUM (A+B) + Cin Cout Cin T0 1 T1 T2 T3 T4 ANSWER : 1101, after 4 clock cycle

Analyzing the circuit : Serial Adder B3 B2 B1 B0 SUM (A+B) + Cin Cout Cin T0 1 T1 T2 T3 T4 Example 2: Reg A : 1011 Reg B : 0101

Analyzing the circuit : Serial Adder B3 B2 B1 B0 SUM (A+B) + Cin Cout Cin T0 1 T1 T2 T3 T4 1 is indicated in Cout ANSWER : 10000, after 4 clock cycle

Serial Vs Parallel Transfers Space Vs Time Trade-off Serial adder is a seq. cct because it includes the carry from FF. but need n clock cycle to complete the addition (Less Space, more Time) Parallel adder is a comb. cct because it needs n FA for n bit operation. Need only one clock cycle to complete the addition. (More Space, less Time) Gives the designer choice. More Space – More cost More Time – More delay (not fast)

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