8259 Programmable Interrupt Controller Interrupts Con.

Features: 8 levels of interrupts. Can be cascaded in master-slave configuration to handle 64 levels of interrupts. Internal priority resolver. Fixed priority mode and rotating priority mode. Individually maskable interrupts. Modes and masks can be changed dynamically. Accepts IRQ, determines priority, checks whether incoming priority>current level being serviced, issues interrupt signal. In 8085 mode, provides 3 byte CALL instruction. In 8086 mode, provides 8 bit vector number. Polled and vectored mode. Starting address of ISR or vector number is programmable. No clock required.

Pin out D0-D7 Bi-directional, tristated, buffered data lines. Connected to data bus directly or through buffers RD-bar Active low read control WR-bar Active low write control A0 Address input line, used to select control register CS-bar Active low chip select CAS0-2 Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on these lines. In slave mode, the PIC reads slave ID no. from master on these lines. It may be regarded as slave-select. SP-bar / EN-bar Slave program / enable. In non-buffered mode, it is SP-bar input, used to distinguish master/slave PIC. In buffered mode, it is output line used to enable buffers INT Interrupt line, connected to INTR of microprocessor INTA-bar Interrupt ack, received active low from microprocessor IR0-7 Asynchronous IRQ input lines, generated by peripherals

Block diagram

ICW1 (Initialization Command Word One) D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 1 LTIM ADI SNGL IC4 D0: IC4: 0=no ICW4, 1=ICW4 required D1: SNGL: 1=Single PIC, 0=Cascaded PIC D2: ADI: Address interval. Used only in 8085, not 8086. 1=ISR's are 4 bytes apart (0200, 0204, etc) 0=ISR's are 8 byte apart (0200, 0208, etc) D3: LTIM: level triggered interrupt mode: 1=All IR lines level triggered. 0=edge triggered D4-D7: A5-A7: 8085 only. ISR address lower byte segment. The lower byte is A7A6A5A4A3A2A1A0

ICW1 of which A7, A6, A5 are provided by D7-D5 of ICW1 (if ADI=1), or A7, A6 are provided if ADI=0. A4-A0 (or A5-A0) are set by 8259 itself

ICW2 (Initialization Command Word Two) Higher byte of ISR address (8085), or 8 bit vector address (8086). A0 1 D7 D6 D5 D4 D3 D2 D1 D0 A15 A14 A13 A12 A11 A10 A9 A8

ICW3 This word is read only when there is more than one 8259 in the system and cascading is used, in which case SNGL = 0. It will load the 8-bit slave register. Master mode: 1 indicates slave is present on that interrupt, 0 indicates direct interrupt Slave mode: ID3 - ID2 - ID1 is the slave ID number. Slave 4 on IR4 has ICW3 = 04h (0000 0100)

ICW4 SFNM: If SFNM = 1 the special fully nested mode is programmed. BUF: If BUF = 1 the buffered mode is programmed. In buffered mode SP’/EN’ pin becomes an enable output and the master/slave determination is by M/S. M/S: If buffered mode is selected: M/S = 1 means the 8259 is programmed to be a master, M/S = 0 means the 8259 is programmed to be a slave. If BUF = 0, M/S has no function. AEOI: If AEOI = 1 the Automatic End Of Interrupt mode is programmed. Mode: Microprocessor mode = 0 sets the 8259 for MCS-80, 85 system operation, Microprocessor Mode = 1 sets the 8259 for 8086 system operation.

Operational Command Words

Operation Command Words After the Initialization Command Words (ICWs) are programmed into the 8259, the chip is ready to accept interrupt requests at its input lines. However, during the 8259 operation, a selection of algorithms can command the 8259 to operate in various modes through the Operation Command Words.

OCW1 OCW1 sets and clears the mask bits in the Interrupt Mask Register (IMR). M7 - M0 represent the eight mask bits. M = 1 indicates the channel is masked, M = 0 indicates the channel is enabled.

OCW2 R, SL, EOI - These three bits control the Rotate and End of Interrupt modes and combinations of the two. L2, L1, L0 - These bits determine the interrupt level acted upon when the SL bit is active.

INTERFACING 8259 WITH 8085 MICROPROCESSOR CASCADING 8259

It requires two internal address A =0 or A = 1. It can be either memory mapped or I/O mapped in the system. The interfacing of 8259 to 8085 is shown in figure is I/O mapped in the system. The low order data bus lines D0-D7 are connected to D0-D7 of 8259. The address line A0 of the 8085 processor is connected to A0 of 8259 to provide the internal address. The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select signal for 8259. The address lines A4, A5 and A6 are used as input to decoder. The control signal IO/M (low) is used as logic high enables for decoder and the address line A7 is used as logic low enable for decoder.

The I/O addresses of 8259 are shown in table

Working of 8259 with 8085 processor First the 8259 should be programmed by sending Initialization Command Word (ICW) and Operational Command Word (OCW). These command words will inform 8259 about the following, Type of interrupt signal (Level triggered / Edge triggered). Type of processor (8085/8086). Call address and its interval (4 or 8) Masking of interrupts. Priority of interrupts. Type of end of interrupts.

Working of 8259 with 8085 processor cont. Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an interrupt through any one of the interrupt lines IR0-IR7 it checks for its priority and also checks whether it is masked or not. If the previous interrupt is completed and if the current request has highest priority and unmasked, then it is serviced. For servicing this interrupt the 8259 will send INT signal to INTR pin of 8085. In response it expects an acknowledge INTA (low) from the processor.

Working of 8259 with 8085 processor cont. When the processor accepts the interrupt, it sends three INTA (low) one by one. In response to first, second and third INTA (low) signals, the 8259 will supply CALL opcode, low byte of call address and high byte of call address respectively. Once the processor receives the call opcode and its address, it saves the content of program counter (PC) in stack and load the CALL address in PC and start executing the interrupt service routine stored in this call address