MacroNET Network Topology ELE-580i PRESENTATION-I 03/13/2003 Canturk ISCI
Introduction MacroNET: Drawbacks: Large area electronics + flexible & deformable <rolled like a window shade> Interactive Map << E-ink (www.eink.com) PowerPaper (www.powerpaper.com) Distributed processing units (light) Interconnect fabric (light) Drawbacks: A-Si over plastic (due to size and flexibility) Low n No p-device No ~CMOS Area ~ x400 of CMOS (~x2500 in Princeton) Currently O(10) T circuits 1/2/2019
PROJECT Definition: Motivation: Related Work: Sparse, Lightweight, Low node degree topology Transistor Budget Direct Network Compute & Route same + buffer=regfile/memory Some extent of path diversity Fault tolerance Motivation: Particular design challenges Tight complexity, fault tolerance Relaxed Latency, performance Related Work: More performance driven Lightweight networks – for on chip processors focus on reducing latency 1/2/2019
Design Cycle Transistor Budget Topology Routing & Compute Node Break the loop: Assume an initial Topology Define compute node Define the nature of Communication and instructions among nodes Acquire a representative Traffic pattern Redefine an appropriate topology Sparse Torus?? Move to CPU modeling: Detailed description (~dataflow) of CPU Back of the envelope Transistor Count Computation Anticipated Constraints: 1000 Ts per CPU Node degree <3 (connectivity??) Transistor Budget Topology Routing & Flow Control Traffic Pattern Compute Node Model Instructions & Communication 1/2/2019
Initialization Topology: mesh (degree = 4!) CPU instructions: Zoom around node(r,c) Dim / brighten Maketop N/S/W/E ( like rotate) Compute distance ** (Directed Routing) Show Places of interest, etc.?? Input style: from sensors Communication – Routing: Instruction dependent Channel Capacity: Infinite (for traffic pattern generation) This setup is very relaxed for traffic pattern generation!! 1/2/2019
CURRENT Status (r,c) (0,0) (1,3) (0,2) (3,3) (1,0) (0,1) (1,2) (3,0) Implementing MacroSIM Need to discuss communications… I.e. zoom (2,1): (r,c) (0,0) (1,3) (0,2) (3,3) (1,0) (0,1) (1,2) (3,0) (2,3) (3,2) (0,0) (0,1) (0,2) (0,3) (0,3) Initial Processor (r,c) (1,0) (1,1) (2,0) (3,1) (2,2) (1,1) (1,2) (1,3) Updated Processor Sent Instruction (2,0) (2,1) (2,1) (2,2) (2,3) Sent ACK Sent ACKed (3,0) (3,1) (3,2) (3,3) Used Channel 1/2/2019