Lecture 3 Simulation and Testbench

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Presentation transcript:

Lecture 3 Simulation and Testbench Advanced Logic Design Lecture 3 Simulation and Testbench

Overview Analog simulation Event-driven logic simulation Signal levels in logic simulation Propagation delay Inertial delay Testbench

Analog Simulation Simulate waveforms Trace every signal at every time point at certain sampling rate Precise Long simulation time v t

Logic Simulation At any moment, most signals are quiescent Very few signal levels At any simulation time, trace only signals with transitions (event) Propagate events from inputs toward outputs In a logic simulator An ordered list of “event-times” At each even time, an event queue is maintained

X and Z a = b = 0: c = Z a = b = 1: c = X Initially, every line is X c 1 b a = b = 0: c = Z a = b = 1: c = X Initially, every line is X X is used in simulation. In real circuit, the value is determined by the circuit

Simulation without Delay X B X A C C D X B D X Y 0 10 20 30 40 50 tsim A = x B = x C = x D = x A = 1 B = 0 B = 1 A = 0 B = 0 C = 1 C = 0 C = 0 D = 0 D = 1 D = 1

Simulation with Delay 0 10 20 30 40 50 tsim 15 A X B X A C D C 3 2 X 13 B D X 0 10 20 30 40 50 15 tsim A = x B = x C = x D = x A = 1 B = 0 B = 1 A = 0 B = 0 C = 1 C = 0 C = 0 D = 0 D = 1 D = 1

Inertial Delay Delay is caused by charging and discharging node capacitors in circuit Gate delay and wire delay Pulse rejection If pulse with is less than delay, the pulse is ignored A C D B

Example of De-scheduling B A C D C 3 2 D B 10 20 30 40 50 T_sim 15 33 35 A=x B=x C=x D=x A=1 B=0 B=1 C=0 D=1 C=1 D=0 A=0 C=1

Testbench Stimulus generator Unit_Under_Test Design_Unit_Test_Bench Response monitor

Some New Keywords initial declares one-shot behaviors $monitor task is used to observe events $time returns simulation time $stop task stops execution and wait for interactive input $finish returns control to operating system

Example of NAND Latch module Nand_Latch_1 (q, qbar, preset, clear); 1 q_pre qbar_pre G1 preset q 1 qbar clear 1 G2 module Nand_Latch_1 (q, qbar, preset, clear); output q, qbar; input preset, clear; nand G1 (q, preset, qbar), G2 (qbar, clear, q); endmodule

Example of Testbench module test_Nand_Latch_1; reg preset, clear; wire q, qbar; Nand_Latch_1 M1 (q, qbar, preset, clear); // Instantiate UUT initial // Create response monitor $monitor ($time, "preset=%b clear=%b q=%b qbar=%b", preset, clear, q, qbar); initial begin // Create DUTB stimulus generator #10 preset = 0; clear = 1; #10 preset = 1; $stop; // Enter . to proceed #10 clear = 0; #10 clear = 1; #10 preset = 0; end #60 $finish; // Finish simulation endmodule G1 preset q 1 qbar clear 1 G2

Simulation Results tsim 0 10 20 30 40 50 tsim 0 10 20 30 40 50 G1 preset preset q 1 1 tsim 0 10 20 30 40 50 clear qbar 1 clear 1 G2 tsim 0 10 20 30 40 50 q 1 0 preset = x clear = x q = x qbar = x 10 preset = 0 clear = 1 q = x qbar = x 11 preset = 0 clear = 1 q = 1 qbar = x 12 preset = 0 clear = 1 q = 1 qbar = 0 20 preset = 1 clear = 1 q = 1 qbar = 0 30 preset = 1 clear = 0 q = 1 qbar = 0 31 preset = 1 clear = 0 q = 1 qbar = 1 32 preset = 1 clear = 0 q = 0 qbar = 1 40 preset = 1 clear = 1 q = 0 qbar = 1 tsim 0 10 20 30 40 50 qbar 1 tsim 0 10 20 30 40 50