Read Delay Simulations

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Presentation transcript:

Read Delay Simulations 65nm STT-RAM Read Delay Simulations

Summary Calibration Pulses Minimum Width: 10ns Pulse Step: 10ns Rise/Fall Time: ~1ns This is causing truncation of the calibration pulses (i.e. they are about 1ns shorter than we thought they were). Voltage Droop 80-120Ω from power ring (depends upon memory bank) 5 Oscillators pull about 3-4mA when running Observed experimentally and in simulation ~300mV drop in supply voltage Explains why the oscillators are running at only 4GHz Read Delay Circuit Offset Compensating for the rise/fall time, the offset is about 0. Measurement accuracy: ±1 count (±250ps)

Spectre Simulation

Matlab Simulation

Multiple Counters