Moving Arrays -- 2 Completion of ideas needed for a general and complete program Final concepts needed for Final DMA

DMA , Copyright M. Smith, ECE, University of Calgary, Canada Tackled today Demonstrating memory to memory DMA Coding DMA DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

When DMA might be useful -- Double Buffering Program Wait for picture 2 memory to fill – video-in Picture 3 comes into memory – background DMA task from input Process picture 2 – place into picture 0 location Picture 4 comes into memory – background DMA task from input Process picture 3 – place into picture 1 location Transmit picture 0 – background DMA task to output Picture 0 comes into memory – background DMA task from input Process picture 4 – place into picture 2 location Transmit picture 1– background DMA task to output Picture 1 comes into memory – background DMA task from input Process picture 0 – place into picture 3 location Transmit picture 2 – background DMA task to output Picture 2 comes into memory – background DMA task from input Process picture 1 – place into picture 4 location Transmit picture 3– background DMA task to output DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

We are only going to look at a simple DMA task Normal code P0  address of start_array[0]; P1  address of final_array[0]; R0  max-value needed to transfer R1  How many values already transferred R1 = 0; LOOP: CC = R0 <= R1 IF CC JUMP DONE: R2 = [P0++]; VERY BIG PIPELINE [P1++] = R2; LATENCY ISSUES JUMP LOOP; MANY INTERNAL PROCESSOR STALLS DONE: WHILE WAIT FOR R2 TO BE Do something else READ, STORED and then TRANSMITTED DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

We are only going to look at a simple DMA task DMA_source_address_register  address of start_array[0]; DMA_destination_address_register  address of final_array[0]; DMA_max_count_register  max-value needed to transfer DMA_count_register  How many values already transferred R1 = 0; LOOP: CC = R0 <= R1 IF CC JUMP DONE: DMA_enable = true R2 = [P0++]; [P1++] = R2; Miminized pipeline issues JUMP LOOP; DONE: Do something else Processor can do something else while DMA is working DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

Write some tests so we know how to proceed -- Test 2 External memory test – arrays in external SDRAM SDRAM -- MANY MEGS AVAILABLE SDRAM addresses hard-coded in this example (use section(“sdram”) ) DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

Write some tests so we know how to proceed -- Test 3 Most probable way to use DMA – Store in SLOW external memory Move to process in FAST internal memory, put back into external SDRAM Addresses hard-coded DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

Some results Code details later Debug Mode Release Mode L1  L1 Internal to Internal 8748 625 L1  L1 DMA 6579 6477 DMA slower SDRAM  SDRAM Extern to External 39132 28200 SDRAM  SDRAM DMA 12175 12090 SDRAM  L1 DMA 5265 4836 SDRAM  L1 DMA L1  SDRAM DMA 9792 9276 DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

Memory to memory move Release Mode DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

New debugging tool Pipeline viewer -- L1  L1 Pipeline viewer runs with the Blackfin SIMULATOR and can show how the processor is actually working in (very very) great detail Every B is a bubble (empty slot) in the pipeline. Once this code gets started then it is reasonably efficient (there are better ways of doing this in ASM) DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

Pipeline viewer SDRAM  SDRAM Every memory access to SDRAM stalls the processor 6 times since external SDRAM is so slow compared to internal L1 memory DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada Key DMA Elements idle( ); // idle; ASM DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada Idle We have the ability to “poll” a flag to determine whether the DMA has finished Instead – we demonstrate the ability to go into “idle” (infinite do-nothing loop) until the “background DMA” causes an interrupt and “wakes up” the system. Once the interrupt occurs, the program automatically moves past the “idle” instruction onto the next instruction! DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

Source DMA – read Destination DMA – write DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada DMA Interrupt ISR Essentially the same as the PF (Lab. 4) or SPI (Lab. 5) interrupts Clear an interrupt status bit so that the interrupt does not keep happening Details needed -- Why D0 and not S0 as well? Set a flag so that main program can continue Was not used in this example code – used idle( ) Which automatically set the processor to sleep until this interrupt happened DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA register detail -- status RO W1C bits Why only Destination DMA status considered? DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada Set up DMA interrupts Similar to set up of PF and SPI SICIMASK reister Details needed ISR address into event table Set the IMASK Set the peripheral mask to allow this sort of interrupt DETAIL – SIC_IAR2 register is a special register that allows us to change the priority of interrupts – see next slide DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada SIC_IAR2 register We have the ability to change the priority level of the DMA Use AND to keep other levels unchanged, and then put in required level. Why is it a good idea to set to level 6, even if system reset value was 6?? DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada How to configure DMA Certain functionality obvious DMA Source channel S0 – starts at address of &start[0]; number to mover size change address by 4 each time – 4 bytes = 1 32-bit word Questions – Why X_MODIFY and not just MODIFY (name of another DMA register)? Why do you need two DMA channels to move things and not just one? DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

Source DMA Configuration register – answers 2 questions S0 – read, 32-bits Stop when done, No interrupt when done Leave disabled Inner (X) and outer (Y) interrupts possible 1D or 2D transfers DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

Destination DMA Configuration register – answers 1 question D0 – read, 32-bits Stop when done, Interrupt when done Inner (X) and outer (Y) interrupts possible 1D or 2D transfers DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada Review Exercises - I Write the overloaded C++ functions void ConfigMDMA(unsigned int* start, unsigned int* finish, int size); void ConfigMDMA(float* start, float* finish, int size) DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada Review Exercises -- II Write the overloaded C++ functions void ConfigMDMA(short int* start, short* finish, int size); void ConfigMDMA(char *start, start* finish, int size) DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada Remaining questions How does DMA work, and why is it better than the normal R0= [P0++]; [P1++] = R0? Why do we need 2 DMA channels? DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada Two different busses in use Working DMA model Source channel Source  FIFO Destination channel FIFO  Destination DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada Tackled today Demonstrating memory to memory DMA Coding DMA DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019

DMA , Copyright M. Smith, ECE, University of Calgary, Canada Information taken from Analog Devices On-line Manuals with permission http://www.analog.com/processors/resources/technicalLibrary/manuals/ Information furnished by Analog Devices is believed to be accurate and reliable. However, Analog Devices assumes no responsibility for its use or for any infringement of any patent other rights of any third party which may result from its use. No license is granted by implication or otherwise under any patent or patent right of Analog Devices. Copyright  Analog Devices, Inc. All rights reserved. DMA , Copyright M. Smith, ECE, University of Calgary, Canada 1/2/2019