Software Vision To Provide Designers The Advantages of…. Methodologies that increase designer productivity Focus on HDL flows Delivering the industry’s fastest clock rates Support for the industry’s biggest devices Commitment to industry standards (EDIF, VHDL, Verilog) Complete, ready to use design solutions Xilinx software vision extends existing design methodologies through development of open systems based on industry standards to maximize both design performance and device utilization. Different designers may not design to the same device or design in the same environment. Xilinx tools are designed to offer maximize performance and productivity through: Advanced software algorithms specifically tuned for Xilinx silicon Powerful integration with advanced EDA vendors Comprehensive CORE Rich implementation tool set 1

Advanced Implementation Technology Utilized in Alliance & Foundation product families Performance Based Compilation Maximizes Clock Rates Fastest compile times for timing driven designs Automatic push button design flows Intuitive graphical user interfaces Powerful tools require very little interaction Complete flows for HDL and schematic designs Auto-interactive control For even greater performance The key to FPGA implementation is to meet the design requirements. Xilinx achieves that with advanced technology that is common to both the Alliance and Foundation Series products. Performance based compilation utilizes this technology along with the industry’s most robust timing constraint language to achieve the design speed in the shortest amount of time. The design flow is simple and automatic. The user interface allows the designer to get a result quickly and easily. If design performance needs to go to the next level, the tools provide the flexibility to meet those goals. In addition to simple effort level settings, an abundance of options are available that control the synthesis, mapping and place and route phases of the process. A graphical floorplanner and FPGA editor can also be used to gain even greater control. 2

Innovative Technology Xilinx features not provided by Altera Design Manager Save previous versions and revisions automatically Support for timing between clocks Allows for more than one clock in a design Multi-cycle clocks Avoid over constraining designs Clock skew Only Xilinx factors in clock skew when determining clock period Turns Engine Achieve up to 25% more performance using workstations on a network Same constraints for timing analysis & place/route Don’t have to specify timing requirements twice Can easily find timing violations Altera timing tools are inadequate since they do not allow you to specify timing between different clock domains or specify multi-cycle paths. In addition, the timing analyzer doesn’t look at the constraints you gave the place and route tools. You must respecify what you want analyzed. Reentrant route allows you to continue routing a design if the run was interrupted or if the timing requirements were close to being met. Altera requires you to start over again with different options. 4

XC4000XL Technology: FASTER By Design MHz Min CLOCK SPEED RUNTIME (34% faster) 70 (16% higher) 60 60 64 MHz (average) 50 50 55 MHz (average) 40 40 41 Min (average) 30 30 27 Min (average) 20 20 10 10 XILINX ALTERA XILINX ALTERA New Xilinx FPGA Implementation Technology Software provides higher system clock speeds and reduced runtimes as compared to Altera MAX+Plus II V8.3 & FLEX10K Design Test Suite (VHDL & Verilog) of actual customer designs ranging from 10K to 100K system gates. (XC4000XL-08)

Alliance Series Roadmap (Shipping!) A1.5 (Shipping!) A2.1 (Early 1999) Improved Implementation Run-Times (up to 6X) Improved Quality of Results New 4KXV, Spartan, 5K, 3K device support Functional Simulation Models (UNISIM) Up to 4X runtime improvements Constraints Editor Floorplanner New Virtex, 9KXL, 4KXLA, SpartanXL device support Official Support for MTI Synplicity Exemplar Synopsys XSI Design Guide. Up to 2X runtime improvements CPLD Floorplanner Next generation high volume architecture Modular Design Offical Support for LMG Smartmodels Quad Motive Timing Analysis This is an overview of the driver for each Foundation release Foundation version numbering convention is reflective of the implementation tool version which is being delivered In 1.5, MTI (Model Tech), Exemplar and Synplicity become tier 1 vendors which means that we now officially test and support the flows. We also now have a Joint Marketing Agreement with Model Tech indicating a much closer product and marketing relationship. 5

Foundation Series Roadmap (Shipping!) F1.5 (Shipping!) F2.1 (Q2 1999) Foundation Express FCS Improved synthesis technology, flows, QOR Verilog Support Improved Implementation Run-Times (up to 6X) Improved Quality of Results New 4KXV, Spartan, 5K, 3K device support Embedded FPGA Express Unified Project Mgmt. HDL Simulation ‘Plug-Ins’ Up to 4X runtime improvements Constraints Editor Floorplanner New Virtex, 9KXL, 4KXLA, SpartanXL device support HDL Centric Design Entry & Project Management Improved Simulator Capacity & Performance Single Push-Button Flows Improved Error Navigation Up to 2X runtime improvements CPLD Floorplanner Next generation high volume architecture This is an overview of the driver for each Foundation release Foundation version numbering convention is reflective of the implementation tool version which is being delivered NOTE: Additional 3rd party tools such as simulators and formal verification tools may be required for 1 million gate flows. 6

1.5 Software Enhancements Directly address customer needs New Device Support 3 FPGA: Virtex, 4KXLA, Spartan XL (XC40110XV, XC40150XV, XC40200XV, XC40250XV) 1 CPLD: 9500XL Ease of Use Improvements Timespecs and Reports Minimum Delays Graphical Constraints Editor In addition to all of the new architectures and devices in the 1.5 release (which is coming mid ‘98), there are a number of enhancements. The two primary ways designers interact with the tools for automatically implemented designs are by entering timespecs and reading reports. Everything else the tool does for them. To improve ease of use, we have improved our timespec language which is by far the most robust in the industry, by making it easier to use with synthesis(new TNM_NET constraint), easier to place global I/O specs instead of requiring individual ones, and easier to create complex timing constraints by grouping. We also have a number of report improvements to increase designers productivity. A summary timing report will automatically be produced by the place and route tools, instead of requiring the running of timing analysis as a separate step, and the output of messages and warnings has been optimized to reduce the volume of text a designer must review. We are adding a graphical Constraints Editor to make using the powerful timespec language easier. 7

Graphical Constraint Entry Guides user to the best constraint methodology Eliminates need for user knowledge of syntax Reduces need for user knowledge of nets and components of the design

1.5 Software Enhancements Faster Runtimes and Higher Performance Continued Runtime Reductions Focus on “sweet spot” density 2-3X faster runtime in place and route More efficient timing for large designs Much faster design translation Up to 8X for large, flat designs Up to 2X for many small input files Extend Maximum Device Performance Fastest Device Speeds Easier to achieve 50 to 100Mhz Production Floorplanner Improvements in runtimes will continue to be a focus in each release. 9

Graphical Floorplanner Add knowledge of the designs structure to increase performance up to 40% Area constraints for modules provide faster runtimes higher performance design changes made easier

1.5 Software More Customer Driven Enhancements Minimum delay reporting For simulation and static timing analysis XC4000XL family is supported in 1.5 Other families to roll out as characterization is compete Automatic pin locking Automatically generate constraints to lock pins to a specific design revision Static timing analysis and back annotated simulation will now support minimum delays so that users can eliminate race conditions in their system. A new feature is being added to allow you to automatically generate pinlocking constraints for your IOs, based on a previous placed and routed design. Pinlocking is a step that every designer must eventually do, and automating this will speed their design process. 11

Future Direction Responding to the Changing Landscape Evolution of FPGA Design Cores, HDL, Design reuse, Behavioral compiler Larger design teams Schematic Single designer Synthesis Single designer Synthesis and Cores Small team TIMELINE The landscape is changing for FPGA design: From schematic to synthesis From a single designer to a design team From discreet design to Cores and design reuse The FPGA tools are evolving to meet those changes with the addition of: Timing driven place and route Support for industry standards like VHDL and Verilog Tighter relationships and integration with leading synthesis vendors And the tools will continue to evolve with new features such as: Being able to compile one module at a time Being able to change one module and preserve the rest of the design with guided compilation Timing Driven PAR HDL Back Annotation Tighter ties with synthesis vendors Module Compile Module Guide Evolution of FPGA Tools 12

Modular Design Xilinx is Leading the Way Facilitates Group Design & Reuse Seamless Integration Between Modules Extension to leading cores solution Modular Time Specs With industry’s best timing constraint language Modular Incremental Compile Extensive R&D investment Designer1 Module Designer2 Module Designer3 Module Design Reuse As designs get larger and people move toward system on a chip device, their designs will not consist of just random gates. They will consist of Cores, modules from old designs, and new modules created by different designers. Integration between these modules is extremely important. The ability to generate timing requirements for each module must be added to the software. By separating the task into modules, each one can be compiles separately which will produce shorter compile times and high performance. The foil above is a good example of how a large design is created. Multiple cores and multiple designers to design portions of the device. Xilinx deliver software solutions that help design, manage, and integrate these modules. Reduces Compile Time & Increases Performance

Modular Design Roadmap Multiple Design Team Support Team Oriented Design Management Module Timing Independence Auto Timing Budgets Auto Linking of Modules Modular Timing Constraints ECO Single Module Flow Features Links to RTL Floorplanning 1 million+ gate capability Increased Performance Reduced Runtime Modular Guide The 2.1 release in 1999 will efficiently handle very large (over 1 million gates) designs. This is accomplished by breaking the design into modules and letting the place and route tools operate on each module as a separate entity. Performance within each module will be optimized and can be much better than if the place and route tools flattened the design. Runtime for large designs will increase more linearly as size increases, instead of the current exponential increases. RTL floorplanners will be able to pass modular information such as area constraints to define physical and logical module boundaries. Incremental design can be accomplished by keeping the unchanged modules intact and only reimplementing the changed module. In the 2.2 release, we are planning on the ability to save each module as a separate entity which can be linked into the full design. This will allow for much faster runtime since unchanged modules do not have to be touched. There will be more capability to define the timing of a single module and to implement that module without knowledge of the rest of the design. ECO (Engineering Change Order) is the ability to make small changes to the design and leave the timing of the rest of the design intact. This can greatly shorten verification time. Team based design will come later and include the design management for various teams and the ability to automatically budget timing across modules and redistribute that timing as modules are finished. 1998 1999 2000 2001 2002

Modular Design in Version 2.1 Floorplanning Detailed and modular physical layout Interface to 3rd party RTL floorplanners Implementation Place and route optimized for modular area constraints Critical timing path optimization within modules Much faster runtime for large designs Guided iterations for synthesis designs Only changed modules have to be re-placed and routed Reduces runtime and verification time for unchanged modules

Compile Time Leadership 50 40 Up to 3X faster than 1.4 30 Minutes* 20 10 2002 Although in some situations a sales person may hesitate to show this slide based on customer perception, the goal of this slide is to take a step toward changing this perception. Xilinx clearly leads, when it comes to high performance design and timing driven compiles, and we are consistently beating our competition at various benchmarks. We may not always win, but we are definitely competitive and are in a good position to lead in many situations. Notes: Average compile time for a 100,000 gate design in 1.3 was only about 400 gates per minute. In 1.4, that improved to 2000 gates per minute and has improved to over 4000 gates per minute in the 1.5 release. It is reasonable to assume that continued compile time improvements will achieve around 6000 gates per minute next year. Assume that CPUs increase at about 2X per year means that 100,000 gates would take slightly over 8 minutes. Plus the fact that module based compile means a linear increase in compile time as gate count increases. Therefore, 1,000,000 = 10 modules of 100,000 gates @ 8 min = 80 minutes. With further advancements, we expect to keep the compile time of 10,000,000 gate designs to under 1 hour by the year 2002. 1998 1999 2000 2001 * 100k System gate designs (400MHz Pentium) And with ... Faster CPUs Faster Compile Times Modular Compile 1999 Goal: 1 Million Gates in under 1.5 hours!

Rapid Time-to-Market Through Guided Designing Existing Design Placed & Routed New Design with Moderate Changes Preserve timing Reduced Runtime Reduced verification time Guided Synthesis Modular design methodology Modular Guided Implementation Guided Synthesis Only re-synthesize new module Retain most of changed module Re-optimize new portions The most efficient way to perform design iterations is through guided design. All logic that has not changed will be preserved and only changed logic has to be recompiled. Not only does this offer much faster runtimes, but makes the design iterations much more predictable. Verification time can also be reduced since most of the design has not changed. Modular Guided Implementation Only re-compile new module Retain most of changed module Place & Route new portions 14

Reduce Your Time-to-Market Using Cores Design from scratch Learn Design Implement Verify Reference design, generic core L D I V Complete Core solution L D I V Time to market advantage of using complete core solutions Months Significant time and risk reduction by using pre-verified Cores Reduced compile time 15

Summary Xilinx programmable Software Solutions for… Gates: 1,500,000 Freq.: 150 MHz+ Gates: 1,000,000 Freq.: 100 MHz+ Gates: 85K Freq.: 65MHz+ 1997 1998 1999 2000 Xilinx programmable Software Solutions for… The best in design performance The best in timing driven runtimes The best HDL design flow support The industry’s most advanced technology Best positioned to deliver the future 17