Jun Chen and Changbo Long

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Presentation transcript:

Jun Chen and Changbo Long Circuit Resynthesis by Pipelining and Simultaneous Retiming and Clock Scheduling Jun Chen and Changbo Long

Background SIS: a sequential circuit synthesis tool developed in UC-Berkeley. Including a re-synthesis package for minimizing clock cycle. (Retiming only) Clock skew scheduling: introducing skew between clock signals that control DFF.

Purpose Improve the re-synthesis package in SIS to further reduce the minimal clock cycle. Simultaneous retiming and clock skew scheduling optimize the clock cycle for the loops. Pipelining the combinational logic to meet the loop bound.

Progress Pipelining: Simultaneous retiming and clock skew scheduling: Under progress

Expected Results and Achievement Apply our method to the retiming result from SIS. Give new clock scheduling for each gate. Give out cut-set of the whole circuit. Give locations of the pipelining DFF. Goals: Reduce the clock cycle of loops by at least 10% compared to the result from SIS retiming package. Reduce the clock cycle of the whole circuit to minimal clock cycle decided above.