Excitation Vectors Input Combinational Logic Memory Output States

RS Latch Q+ = S + R’ Q Two Problems: R=S= 1 Not allowed, Data is transparent

The D Latch Problem: Level sensitive

JK Latch : Universal, Level sensitive, Timing Constraints due to feed back.

Master Slave Flip Flop Edge sensitive,Set up and Hold time

Master Slave Flip Flop Edge sensitive,-Falling Edge Set Up and Hold Time constraints Path to setup data Master Slave D D Q Q Q D D D Latch Latch Q C C C Path to hold data D C Q

Edge triggered Flip Flop: Set up and Hold time Constraints

Edge Triggered, D Flip Flop NAND1 S Q NAND2 NAND5 clk R NAND3 NAND6 D NAND4 reset

When CLK changes from 0 to 1 Case1, D=0: tsetup= t4, thold=t3 Case2, D=1 tsetup=t4 + t1 thold= t2 clk D reset Q NAND1 NAND2 NAND3 NAND4 NAND5 NAND6 S R

When CLK changes from 0 to 1 Case1, D=0: tsetup= t4, thold=t3 reset Q NAND1 NAND2 NAND3 NAND4 NAND5 NAND6 S R Path for hold Path for set up

When CLK changes from 0 to 1 Case2, D=1 tsetup=t4 + t1 thold= t2 Path to set up clk D reset Q NAND1 NAND2 NAND3 NAND4 NAND5 NAND6 S R Path to hold

D Flip Flop