Review Lectures Mar. 31 – April 9 2003 Note:.

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Presentation transcript:

Review Lectures Mar. 31 – April 9 2003 Note:

Assignments Ass1: 2.1, 2.2, 2.5, 2.6, 2.7, 2.9 Ass2: 3.1, 3.3, 3.4, 3.5, 3.6, 3.7 Ass3: 3.9 (switch logic), 3.13, 3.15, 3.16, 3.17, 3.23, 5.1, 5.4 VHDL and Verilog: one-bit full-adder Note:

Review Chapter 1: Overview Chapter 2 : 2.1, 2.2 Fabrication steps 2.3.1 – 2.3.4 Simple transistor model and tub tie and latch up current, voltage and gate capacitance 2.4 wires and vias 2.5-2.6 Design rules and stick diagram Note:

Midterm Review (cont’d) 3. Chapter 3 3.1, 3.2 Combination logic 3.3 – 3.8 Noise margin, delay, power consumption driving large load, switch logic, Peseudo-nMOS, Domino, RC transmission line Chapter 5: 5.1-5.2 latch and flip-flop 5. Notes: Scale, yield, routing, simulation, VHDL/Verilog, adder, memory, FPGA Note:

Examples Note:

Final TBA Note: