Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs Publisher/Conf: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI)

Slides:



Advertisements
Similar presentations
Low power 32-bit bus with inversion encoding Wei Jiang ELEC 6270.
Advertisements

A HIGH-PERFORMANCE IPV6 LOOKUP ENGINE ON FPGA Author : Thilan Ganegedara, Viktor Prasanna Publisher : FPL 2013.
An On-Chip IP Address Lookup Algorithm Author: Xuehong Sun and Yiqiang Q. Zhao Publisher: IEEE TRANSACTIONS ON COMPUTERS, 2005 Presenter: Yu Hao, Tseng.
MACHINE-INDEPENDENT VIRTUAL MEMORY MANAGEMENT FOR PAGED UNIPROCESSOR AND MULTIPROCESSOR ARCHITECTURES R. Rashid, A. Tevanian, M. Young, D. Golub, R. Baron,
Image Processing - Segmentation Variational Models Osher-Sethian Level-Set Framework + topologically flexible Osher-Sethian Level-Set Framework + topologically.
MultiNoC  What is it?  a programmable on-chip multiprocessing platform using a network-on-chip (NoC) as communication media  To whom is it addressed?
Conference title 1 Addressing heterogeneity, failures and variability in high-performance NoCs José Duato Parallel Architectures Group (GAP) Technical.
KARL NADEN – NETWORKS (18-744) FALL 2010 Overview of Research in Router Design.
Reporter: Bo-Yi Shiu Date: 2011/05/27 Virtual Point-to-Point Connections for NoCs Mehdi Modarressi, Arash Tavakkol, and Hamid Sarbazi- Azad IEEE TRANSACTIONS.
Miguel Gorgues, Dong Xiang, Jose Flich, Zhigang Yu and Jose Duato Uni. Politecnica de Valencia, Spain School of Software, Tsinghua University, China, Achieving.
1 A Heuristic and Hybrid Hash- based Approach to Fast Lookup Author: Gianni Antichi, Andrea Di Pietro, Domenico Ficara, Stefano Giordano, Gregorio Procissi,
Chia-Yen Hsieh Laboratory for Reliable Computing Microarchitecture-Level Power Management Iyer, A. Marculescu, D., Member, IEEE IEEE Transaction on VLSI.
Review for Test 2 i206 Fall 2010 John Chuang. 2 Topics  Operating System and Memory Hierarchy  Algorithm analysis and Big-O Notation  Data structures.
> >
Implementation of a Tapestry Node: The main components: The core router, utilizes the routing and object reference tables to handle messages, The node.
Power Aware Solutions for NoC Architecture Yaniv Ben-Itzhak Noc Seminar Winter 08.
CS294-6 Reconfigurable Computing Day 14 October 7/8, 1998 Computing with Lookup Tables.
Physical Implementation 1)Manufactured Integrated Circuit (IC) Technologies 2)Programmable IC Technology 3)Other Technologies Manufactured IC Technologies.
Network-on-Chip: Communication Synthesis Department of Computer Science Texas A&M University.
Design and Implementation of VLSI Systems (EN1600) lecture05 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.
1 times table 2 times table 3 times table 4 times table 5 times table
GOOD MORNING.
ERD and Memory Architectures Paul Franzon Department of Electrical and Computer Engineering
High Performance Embedded Computing © 2007 Elsevier Lecture 16: Interconnection Networks Embedded Computing Systems Mikko Lipasti, adapted from M. Schulte.
ECE 526 – Network Processing Systems Design Network Processor Architecture and Scalability Chapter 13,14: D. E. Comer.
José Vicente Escamilla José Flich Pedro Javier García 1.
PARALLEL TABLE LOOKUP FOR NEXT GENERATION INTERNET
A Low-Power CAM Design for LZ Data Compression Kun-Jin Lin and Cheng-Wen Wu, IEEE Trans. On computers, Vol. 49, No. 10, Oct Presenter: Ming-Hsien.
Programmable Logic Devices
MOTION ESTIMATION IMPLEMENTATION IN VERILOG
Area: VLSI Signal Processing.
1 A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, and Tsai-Wen.
ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)
Axel Jantsch 1 Networks on Chip Axel Jantsch 1 Shashi Kumar 1, Juha-Pekka Soininen 2, Martti Forsell 2, Mikael Millberg 1, Johnny Öberg 1, Kari Tiensurjä.
A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing Author: Satendra Kumar Maurya, Lawrence T. Clark Publisher: IEEE TRANSACTIONS.
Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.
1 Presenter: Min Yu,Lo 2015/12/21 Kumar, S.; Jantsch, A.; Soininen, J.-P.; Forsell, M.; Millberg, M.; Oberg, J.; Tiensyrja, K.; Hemani, A. VLSI, 2002.
An Introduction to VLSI (Very Large Scale Integrated) Circuit Design
Author: Haoyu Song, Murali Kodialam, Fang Hao and T.V. Lakshman Publisher/Conf. : IEEE International Conference on Network Protocols (ICNP), 2009 Speaker:
TEMPLATE DESIGN © A Comparison-Free Sorting Algorithm Saleh Abdel-hafeez 1 and Ann Gordon-Ross 2 1 Jordan University of.
$100 $200 $300 $400 $500 $100 $200 $300 $400 $500 $100 $200 $300 $400 $500 $100 $200 $300 $400 $500 $100 $200 $300 $400 $500 $100 $200 $300.
EE415 VLSI Design THE INVERTER [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Tables Learning Support
Ultra-High Throughput Low-Power Packet Classification Author: Alan Kennedy and Xiaojun Wang Accepted by IEEE Transactions on VLSI.
A NOVEL LEVEL-BASED IPV6 ROUTING LOOKUP ALGORITHM Author: Xiaohong Huang, Xiaoyu Zhao, Guofeng Zhao, Wenjian Jiang, Dongqu Zheng, Qiong Sun and Yan Ma.
FPGA Field Programmable Gate Arrays Shiraz University of shiraz spring 2012.
A Multi-Mode Selectable DC-DC Converter for Ultralow Power Circuits Ernie Bowden Doug Sorenson.
11 SAP & SQL Server 2005 Reporting Services (with Dundas Map) Integration Microsoft Corporation SAP-Microsoft Competence Center (Tokyo) Microsoft Corporation.
FPGA IMPLEMENTATION OF TCAM Under the guidance of Dr. Hraziia Presented By Malvika ( ) Department of Electronics and Communication Engineering.
Field Programmable Gate Arrays
Author: Heeyeol Yu; Mahapatra, R.; Publisher: IEEE INFOCOM 2008
Random access memory.
Efficient Pattern Matching Algorithm for Memory Architecture
AN ON-CHIP IP ADDRESS LOOKUP ALGORITHM
VLSI INTRODUCTION - Prof. Rakesh K. Jha
Toward Advocacy-Free Evaluation of Packet Classification Algorithms
Electronics for Physicists
Downsizing Semiconductor Device (MOSFET)
Hire Toyota Innova in Delhi for Outstation Tour
Times Tables.
NETWORK-ON-CHIP HARDWARE ACCELERATORS FOR BIOLOGICAL SEQUENCE ALIGNMENT Author: Souradip Sarkar; Gaurav Ramesh Kulkarni; Partha Pratim Pande; and Ananth.
Experiment Evaluation
Multiprocessor network topologies
Physical Implementation Manufactured IC Technologies
Downsizing Semiconductor Device (MOSFET)
Operating Systems Placement Algorithm Alok Kumar Jagadev.
Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt,
3 times tables.
6 times tables.
High-Performance Pattern Matching for Intrusion Detection
Presentation transcript:

Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs Publisher/Conf: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Aauthors: Andres Mejia, Maurizio Palesi, José Flich, Shashi Kumar

Perceived higher cost , higher power consumption, and lack of scalability when implementing the tables in SRAM memories. As the system increases in size, the memory requirements for building such routing tables also increase

FSM-based switch (FSM) implements the Dimension Order Routing (DOR) routing algorithm. Table-based switch (TB) A table of N * 2 * d bits for the table-based implementation. Region-based switch (RB) 16 regions were used for the region-based switch Mapped on a 90-nm technology library from TSMC.

In terms of area and power dissipation consumption, a region-based switch is less than 4% more expensive than an FSM-based switch and more than 55% cheaper than a table-based switch In terms of power consumption, a region-based switch is less than 1% more expensive than an FSM-based switch and more than 45% cheaper than a table-based switch.