Register Allocation Hal Perkins Autumn 2005

Slides:



Advertisements
Similar presentations
Register Allocation COS 320 David Walker (with thanks to Andrew Myers for many of these slides)
Advertisements

Register Allocation Consists of two parts: Goal : minimize spills
Compiler Support for Superscalar Processors. Loop Unrolling Assumption: Standard five stage pipeline Empty cycles between instructions before the result.
Register Usage Keep as many values in registers as possible Register assignment Register allocation Popular techniques – Local vs. global – Graph coloring.
P3 / 2004 Register Allocation. Kostis Sagonas 2 Spring 2004 Outline What is register allocation Webs Interference Graphs Graph coloring Spilling Live-Range.
Register Allocation Zach Ma.
Register Allocation CS 320 David Walker (with thanks to Andrew Myers for most of the content of these slides)
1 CS 201 Compiler Construction Machine Code Generation.
11/21/2002© 2002 Hal Perkins & UW CSEO-1 CSE 582 – Compilers Instruction Scheduling Hal Perkins Autumn 2002.
Register Allocation CS 671 March 27, CS 671 – Spring Register Allocation - Motivation Consider adding two numbers together: Advantages: Fewer.
6/9/2015© Hal Perkins & UW CSEU-1 CSE P 501 – Compilers SSA Hal Perkins Winter 2008.
1 CS 201 Compiler Construction Lecture 12 Global Register Allocation.
Improving code generation. Better code generation requires greater context Over expressions: optimal ordering of subtrees Over basic blocks: Common subexpression.
Register Allocation (Slides from Andrew Myers). Main idea Want to replace temporary variables with some fixed set of registers First: need to know which.
1 Register Allocation Consists of two parts: –register allocation What will be stored in registers –Only unambiguous values –register assignment Which.
Prof. Bodik CS 164 Lecture 171 Register Allocation Lecture 19.
Code Generation for Basic Blocks Introduction Mooly Sagiv html:// Chapter
Register Allocation (via graph coloring)
U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science Emery Berger University of Massachusetts, Amherst Advanced Compilers CMPSCI 710.
Register Allocation (via graph coloring). Lecture Outline Memory Hierarchy Management Register Allocation –Register interference graph –Graph coloring.
1 Liveness analysis and Register Allocation Cheng-Chia Chen.
Improving Code Generation Honors Compilers April 16 th 2002.
Improving code generation. Better code generation requires greater context Over expressions: optimal ordering of subtrees Over basic blocks: Common subexpression.
4/29/09Prof. Hilfinger CS164 Lecture 381 Register Allocation Lecture 28 (from notes by G. Necula and R. Bodik)
Spring 2014Jim Hogg - UW - CSE - P501P-1 CSE P501 – Compiler Construction Register allocation constraints Local allocation Fast, but poorer code Global.
1 October 18, October 18, 2015October 18, 2015October 18, 2015 Azusa, CA Sheldon X. Liang Ph. D. Azusa Pacific University, Azusa, CA 91702, Tel:
U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT Optimizing Compilers CISC 673 Spring 2009 Register Allocation John Cavazos University.
Local Register Allocation & Lab Exercise 1 Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp.
1 CS 201 Compiler Construction Introduction. 2 Instructor Information Rajiv Gupta Office: WCH Room Tel: (951) Office.
Register Usage Keep as many values in registers as possible Keep as many values in registers as possible Register assignment Register assignment Register.
Register Allocation CS 471 November 12, CS 471 – Fall 2007 Register Allocation - Motivation Consider adding two numbers together: Advantages: Fewer.
2/22/2016© Hal Perkins & UW CSEP-1 CSE P 501 – Compilers Register Allocation Hal Perkins Winter 2008.
Single Static Assignment Intermediate Representation (or SSA IR) Many examples and pictures taken from Wikipedia.
Global Register Allocation Based on
Code Optimization.
Optimizing Compilers Background
The compilation process
Register Allocation Hal Perkins Autumn 2009
Local Register Allocation & Lab Exercise 1
Optimization Code Optimization ©SoftMoore Consulting.
Main Memory Management
Intermediate Representations Hal Perkins Autumn 2011
CSCI1600: Embedded and Real Time Software
Topic 10: Dataflow Analysis
Register Allocation Hal Perkins Autumn 2011
Instruction Scheduling Hal Perkins Summer 2004
Intermediate Representations
Introduction to Code Generation
Wrapping Up Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 412 at Rice University have explicit.
Instruction Scheduling Hal Perkins Winter 2008
CS 201 Compiler Construction
CS 201 Compiler Construction
Intermediate Representations
Register Allocation Hal Perkins Summer 2004
Exam Topics Hal Perkins Autumn 2009
Final Code Generation and Code Optimization
Local Register Allocation & Lab Exercise 1
Lecture 16: Register Allocation
Instruction Scheduling Hal Perkins Autumn 2005
Optimization 薛智文 (textbook ch# 9) 薛智文 96 Spring.
Lecture 17: Register Allocation via Graph Colouring
Target Code Generation
CSE P 501 – Compilers SSA Hal Perkins Autumn /31/2019
Instruction Scheduling Hal Perkins Autumn 2011
CSCI1600: Embedded and Real Time Software
(via graph coloring and spilling)
Exam Topics Hal Perkins Winter 2008
CS 201 Compiler Construction
CS 201 Compiler Construction
Presentation transcript:

Register Allocation Hal Perkins Autumn 2005 CSE P 501 – Compilers Register Allocation Hal Perkins Autumn 2005 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Agenda Register allocation constraints Top-down and bottom-up local allocation Global allocation – register coloring Credits: Adapted from slides by Keith Cooper, Rice University 1/11/2019 © 2002-05 Hal Perkins & UW CSE

k Intermediate code typically assumes infinite number of registers Real machine has k registers available Goals Produce correct code that uses k or fewer registers Minimize added loads and stores Minimize space needed for spilled values Do this efficiently – O(n), O(n log n), maybe O(n2) 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Register Allocation Task At each point in the code, pick the values to keep in registers Insert code to move values between registers and memory No additional transformations – scheduling should have done its job Minimize inserted code, both dynamically and statically 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Allocation vs Assignment Allocation: deciding which values to keep in registers Assignment: choosing specific registers for values Compiler must do both 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Basic Blocks A basic block is a maximal length segment of straight-line code (i.e., no branches) Significance If any statement executes, they all execute Barring exceptions or other unusual circumstances Execution totally ordered Many techniques for improving basic blocks – simplest and strongest methods 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Local Register Allocation Transformation on basic blocks Produces decent register usage inside a block Need to be careful of inefficiencies at boundaries between blocks Global register allocation can do better, but is more complex 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Allocation Constraints Allocator typically won’t allocate all registers to values Generally reserve some minimal set of registers F used only for spilling (i.e., don’t dedicate to a particular value 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Liveness A value is live between its definition and use. Find definitions (x = …) and uses ( … = … x …) Live range is the interval from definition to last use Can represent live range as an interval [i,j] in the block 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Top-Down Allocator Idea Algorithm Keep busiest values in a dedicated registers Use reserved set, F, for the rest Algorithm Rank values by number of occurrences Allocate first k-F values to registers Add code to move other values between reserved registers and memory 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Bottom-Up Allocator Idea Algorithm Replacement Focus on replacement rather than allocation Keep values used “soon” in registers Algorithm Start with empty register set Load on demand When no register available, free one Replacement Spill value whose next use is farthest in the future Prefer clean value to dirty value Sound familiar? 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Bottom-Up Allocator Invented about once per decade Sheldon Best, 1955, for Fortran I Laslo Belady, 1965, for analyzing paging algorithms William Harrison, 1975, ECS compiler work Chris Fraser, 1989, LCC compiler Vincenzo Liberatore, 1997, Rutgers Will be reinvented again, no doubt Many arguments for optimality of this 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Global Register Allocation A standard technique is graph coloring Use control and dataflow graphs to derive interference graph Nodes are virtual registers (the infinite set) Edge between (t1,t2) when t1 and t2 cannot be assigned to the same register Most commonly, t1 and t2 are both live at the same time Can also use to express constraints about registers, etc. Then color the nodes in the graph Two nodes connected by an edge may not have same color If more than k colors are needed, insert spill code Disclaimer: this works well if there are “enough” registers – not necessarily good on x86 machines 1/11/2019 © 2002-05 Hal Perkins & UW CSE

Coming Attractions Dataflow and Control flow analysis Overview of optimizations 1/11/2019 © 2002-05 Hal Perkins & UW CSE