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Presentation transcript:

Princess Sumaya University 4241 - Digital Logic Design Read Only Memory (ROM) A block diagram of a ROM consisting of k inputs and n outputs is shown below. The inputs provide the address for memory, and the outputs give the data bits of the stored word that is selected by the address. The number of words in a ROM is determined from the fact that k address input lines are needed to specify 2k words. Number of words Size of word

Princess Sumaya University 4241 - Digital Logic Design Read Only Memory (ROM) Draw a 32  8 ROM. The unit consists of 32 words of 8 bits each.

Read Only Memory (ROM)

Read Only Memory (ROM) Inputs outputs . I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 1 0 1 1 0 1 1 0 0 0 0 0 0

Read Only Memory (ROM) Example 7.1: Design a combinational circuit using a ROM. The circuit accepts a three-bit number and outputs a binary number equal to the square of the input number. (minimize the ROM if possible)

Read Only Memory (ROM) Example 7.1: Design a combinational circuit using a ROM. The circuit accepts a three-bit number and outputs a binary number equal to the square of the input number. We need a ROM with a size = 8  4

Read Only Memory (ROM)

Programmable Logic Devices

Programmable Logic Array (PLA) F1=AB\+AC+A\BC\ F2=(AC+BC)\

Programmable Logic Array (PLA) Example 7.2 :Implement the following two Boolean functions with a PLA: F1(A, B, C) = (0,1,2,4) F2(A, B, C) = (0,5,6,7) F1 F2 F1= A\B\+A\C\+B\C\ F2= AB+AC+A\B\C\ F1= (AB+AC+BC)\ F2= (A\B+A\C+AB\C\)\

Programmable Logic Array F1= (AB+AC+BC)\ F2= AB+AC+A\B\C\ AB AC BC A\B\C\

16 14

2^15

Without minimizing With minimizing

Without minimizing

B) With minimizing