EECS 465: Digital Systems Design Lecture Notes #3 Logic Design Using Compound Components: Multiplexers SHANTANU DUTT Department of Electrical and Computer Science University of Illinois, Chicago Phone: (312) 355-1314; e-mail: dutt@eecs.uic.edu URL: http://www.eecs.uic.edu/~dutt

Logic Design Using Multiplexers A Transmission Gate ( T-Gate ) Out Steering gate. In=B A When A=1, ‘In’ is “Steered” to ‘Out’. [I.e., the T-gate conducts] Thus Out = B when A=1 Out = AB In Out Symbolic for T-gate: A A is the control input (CI) Normal CI connected to A Bubbled CI connected to T-gate conducts when A=1.

Reversing the connection of A: A bubble CI A normal CI In Out T-gate conducts when A=0. Multiplexer (MUX) Design: A 2:1 MUX. S Out I0 I0 Z Z 2:1 MUX I1 Out I1 S S Z= I0 when S=0 Z= I1 when S=1

Generalization of the TT: S Z S Z 0 1 1 1 0 1 1 0 S Z 1 1 0 0 = S S Z 0 I0 1 I1 is the function implemented by the above 2:1 MUX. Thus, the 2:1 MUX can also be implemented by logic gates: I0 z 2:1 MUX : S I1

A 2:1 MUX selects input Ii if S0 = I [If S0 = 0, Z = I0 # of inputs to a MUX is always a power of 2. I0 The same can be said about a 4:1 MUX: Input Ii is selected (Z=Ii) if S1S0 combination represents the number i in binary. Z I1 4:1 MUX I2 I3 S1 S0

# of data inputs (Iis) is 2n # of control I/Ps = n [If S1S0 = 00 (#0), Z = Io S1S0 = 01 (#1), Z = I1 S1S0 = 10 (#2), Z = I2 S1S0 = 11 (#3), Z = I3] S1 S0 Z 0 0 I0 0 1 I1 1 0 I2 1 1 I3

I0 I1 Z 2n : 1 Sn-1 S1 S0 In general for a 2n:1 MUX with control signals/inputs Sn-1 ··· S1S0 & “data” inputs I0, ···, , Z = Ii when Sn-1 ··· S1S0 combination represents #i in binary.

Construction of MUXes: • Saw the design of a 2:1 MUX using T-gates, as well as logic gates •A 4:1 MUX can be hierarchically constructed using 2:1 MUXes. I0 2:1 MUX I1 I0 Z 2:1 MUX Z S0 I1 4:1 MUX I2 I2 2:1 MUX I3 S1 I3 MSB S0 S1 S0 LSB of control variables

When S0=0, I0, I2 get selected at the 1st level, i.e., Input w/ 0 in LSB. When S0=1, I1, I3 (LSB=1) get selected at the 1st level. If S0 = 0, I0, I2, become the 0th & 1st inputs to the next level. At the next level, the I/P order # is determined by the rest of the bits of their index after stripping off the LSB. Thus I0 I0 I2 I1 At level 2 0 0 (# 0) 1 0 (# 2) strip away for the 2nd level inputs.

Thus the design works as a 4:1 MUX. Z= I0 of level 2 (I0 of level 1), S1=0. = I1 of level 2 (I2 of level1) if S1=1. I0 I2 I0 I1 Level 2 From level 1 S0=0 strip 0 1 I0 I1 Z I1 I3 2:1 MUX Z= I0 of Level 2 (I1 of Level1) if S1=0 = I1 of level 2 (I3 of level 1) if S1=1 Level 1 1 1 strip S1 S0=1 Thus the design works as a 4:1 MUX.

An 8:1 MUX is designed similarly. 2:1 MUX 8:1 MUX I1 S0 I2 I2 2:1 MUX 4:1 MUX I3 S2 S1 S0 I4 S0 General Design of a 2n :1 MUX I4 I4 2:1 MUX I5 2:1 S2 I0 S1 S0 S0 I6 I6 2n:1 MUX 2:1 MUX 2n-1 :1 MUX 2:1 2n-1 2:1 MUXes I7 S0 S0 Sn-1 S0 2:1 Sn-1 S1 S0

Using MUXes to Realize Logic Circuits Example: -- Use A,B,C as control inputs to an 8:1 MUX. -- Treat the data inputs I0, ···, I7 as possible minterms of f: Input Ii is a minterm if #i appears in the  m notation of f. If Ii is a minterm of f, it should be connected to a ‘1’, otherwise it should be connected to a ‘0’. 1 I0 I1 I2 I3 I4 I5 I6 I7 8:1 MUX f S2 S1 S0 A B C

A 3-variable function can always be implemented by an 8:1 MUX. Interestingly, a 3-var. function can also always be implemented by a 4:1 MUX. Example f(A,B,C) =  m(0,2,6,7) • Select any 2 variables, say, A,B, for the 2 control inputs • In a 3-var. K-map, group together squares into 2-squares in which the other variable C varies, but A,B remains constant. •Form implicants 2-square only within 2-squares and write out the function AB 00 01 11 10 C 1 1 1 1 1 AB •

• The function now is in terms of combinations of A, B ANDed with either C, , 1, or 0 Note: 0 is ANDed with an A,B combination (e.g., above) when the 2-square corresponding to that combination does not have any 1’s, i.e., when none of the product terms obtained from the K-map in the above manner has that combination of A, B in them. • Connect either C, , 1, 0 to the appropriate data input corresponding to the A,B combination they are ANDed with in the expression for f. • Thus • Note that a 4:1 MUX implements the function Thus for the above f, and

-- A general n-variable function f(An-1, An-2, ···, A0) A B f f 4:1 MUX 1 0 0 0 1 1 0 0 1 1 1 1 2 S1 S0 3 A B -- A general n-variable function f(An-1, An-2, ···, A0) Implementation possible using a 2n: 1 MUX (w/o requiring any extra gates)? Yes. Implementation possible using a 2n-1: 1 MUX (w/o requiring any extra gates) ? Yes.

E.g.: A 4-var. function f(A,B,C,D) Choose A, B, C as the control inputs AB CD 00 01 11 10 1 1 00 01 1 2 3 4 5 6 7 1 f 1 11 10 1 1 1 A B C

-- In general, a 2i : 1 MUX, where i < n-1, can be used to implement an n-var. function f(An-1, ••• ,A0) by choosing any i variables, say, Ai-1, ••• , A0 ( This is just an example of i variables; you can choose any i of the n variables) as the control inputs of the MUX. However, for i < n-1, extra logic gates may be required. -- Then express f in terms of all combinations of Ai-1, •••, A0 as Where is a function of An-1,•••,Ai that ANDs with the kth product term of variables Ai-1, •••, A0 that represents the binary # k,

-- Thus we get the implementation: g0(An-1,···, Ai+1) Where each gk may need extra logic gates for its implementation. 2i:1 MUX Ai-1 A0 -- The trick is to choose the “right” i variables so that the total # of logic gates needed for the gk’s is minimum.

E.g.: 4-var. function f(A,B,C,D) ; n=4. Let i=2 00 01 11 10 1 1 00 01 1 4-squares where A,B=constant. 11 10 1 1 1 -- For i=2 (2 control variables from A,B,C,D for a 4:1 MUX), the K-map needs to be partitioned into groups of 4-squares, such that within each 4-square the 2 control variables are constant.

-- Note that “PIs” can only be formed within each 4-square, i. e -- Note that “PIs” can only be formed within each 4-square, i.e., groups of squares in which the control vars. are constant (constant areas). -- To min. # of gates, choose the 2 control vars such that the largest-size implicants & the smallest # of them can be formed in its set const. areas. -- A study of the 1’s in the above K-map tells us that this is achieved by the set of 4-squares that are the columns of the K-map, i.e., for control variables A, B. -- Then, in each constant-area, form the SOP sub-expression for all the MTs in that area, just like in a full K-Map (i.e., for all “PIs” in each area, determine and select all “EPIs” in that area, cover remaining MTs in that area by the least-cost set of the remaining “PIs”). -- Grouping 1’s only within the constant areas (4-squares in this ex.) we get over all constant areas, i.e., all combinations of A, B, the expression: A B 1 2 3 4:1 MUX S1 S0 f C Implementation: No logic gates needed! (NOTE: This will not always be the case)

-- If we had chosen A,C as the control variables, then the 4-squares would have looked as follows AB CD 00 01 11 10 1 1 00 01 1 11 10 1 1 1 -- Grouping 1’s only within the 4-squares, we get 4 terms and : all are essential.

-- We thus obtain f in terms of all combinations of A, C as f 4:1 MUX 1 B 2 S1 S0 3 A C -- Thus choosing A,C as control variables, results in 2 extra gates compared to choosing A, B.