Dynamic Pipeline Structure

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Presentation transcript:

Dynamic Pipeline Structure I-Cache fetch front end (in order) instr. queue registers ROB decode/disp. commit integer RS fp RS memory RS store buffer issue issue issue retire back end (out of order) int/br unit fp unit ld/st unit D-Cache finish finish finish forwarding bus

Data Structures (ARF/RRF) RS data rr# data1 rr#1 data2 rr#2 opcode R0 6 R1 2 R2 10 R3 8 RRF data valid X 1 2 3 R0B instr addr ar# rr# exception Finished tail head

Data Structures (RAT/PRF) RS ar# rr# data1 pr#1 data2 pr#2 opcode pr# R0 R1 1 R2 2 R3 3 PRF data valid 6  1 2 10 3 8 4 X 5 7 freelist: 4, 5, 6, 7 R0B instr addr ar# rr# exception Finished tail head

Data Structures (RAT/PRF) Dispatch ADD R2,R0,R3 RAT RS ar# rr# data1 pr#1 data2 pr#2 opcode pr# R0 6 8 + 4 R1 1 R2 2 R3 3 PRF data valid 6  1 2 10 3 8 4 X 5 7 freelist: 4, 5, 6, 7 \ 4 R0B instr addr ar# rr# exception Finished tail head 00000000 2 4 x \

Data Structures (RAT/PRF) Dispatch MUL R1,R0,R2 RAT RS ar# rr# data1 pr#1 data2 pr#2 opcode pr# R0 6 8 + 4 R1 1 * 5 R2 2 R3 3 PRF data valid 6  1 2 10 3 8 4 X 5 7 freelist: 4, 5, 6, 7 \ 5 \ 4 R0B instr addr ar# rr# exception Finished tail head 00000000 2 4 x 00000004 1 5 \ \

Data Structures (RAT/PRF) Dispatch ADD R2,R2,R3 RAT RS ar# rr# data1 pr#1 data2 pr#2 opcode pr# R0 6 8 + 4 R1 1 * 5 R2 2 R3 3 PRF data valid 6  1 2 10 3 8 4 X 5 7 freelist: 4, 5, 6, 7 \ 5 \ 4 \ 6 R0B instr addr ar# rr# exception Finished tail head 00000000 2 4 x 00000004 1 5 00000008 6 \ \ \

Data Structures (RAT/PRF) Dispatch MUL R3,R2,R1 RAT RS ar# rr# data1 pr#1 data2 pr#2 opcode pr# R0 6 8 + 4 R1 1 * 5 R2 2 R3 3 7 PRF data valid 6  1 2 10 3 8 4 X 5 7 freelist: 4, 5, 6, 7 \ 5 \ 4 \ 6 \ 7 R0B instr addr ar# rr# exception Finished tail head 00000000 2 4 x 00000004 1 5 00000008 6 0000000C 3 7 \ \ \ \

Data Structures (RAT/PRF) Finish ADD R2,R0,R3 RAT RS ar# rr# data1 pr#1 data2 pr#2 opcode pr# R0 6 8 + 4 R1 1 14 * 5 R2 2 R3 3 7 PRF data valid 6  1 2 10 3 8 4 14 5 X 7 freelist: 4, 5, 6, 7 \ 5 \ \ 4 \ 6 \ \ 7 R0B instr addr ar# rr# exception Finished tail head 00000000 2 4 x 00000004 1 5 00000008 6 0000000C 3 7 \ \ \ \

Data Structures (RAT/PRF) Complete ADD R2,R0,R3 RAT RS ar# rr# data1 pr#1 data2 pr#2 opcode pr# R0 R1 1 6 14 * 5 R2 2 8 + R3 3 7 PRF data valid 6  1 2 10 3 8 4 14 5 X 7 freelist: 4, 5, 6, 7 \ 5 \ 4 \ 4 \ 6 \ 7 R0B instr addr ar# rr# exception Finished tail head 00000004 1 5 x 00000008 2 6 0000000C 3 7 \ \ \ \ , 2

Data Structures (RAT/PRF delayed read) RS ar# rr# pr#1 valid pr#2 opcode pr# R0 R1 1 R2 2 R3 3 PRF data valid 6  1 2 10 3 8 4 X 5 7 freelist: 4, 5, 6, 7 R0B instr addr ar# rr# exception Finished tail head