Typical STD Cell Library Errors

Slides:



Advertisements
Similar presentations
Registers and Counters
Advertisements

4/14/2015Fractal Technologies Confidential Fractal Technologies Validation Software & Services.
1 COMM 301: Empirical Research in Communication Lecture 15 – Hypothesis Testing Kwan M Lee.
4/16/2015Fractal Technologies Confidential Fractal Technologies Validation checks for: -Standard cell Libraries -IO lib and IP (Design Formats)
Waiving Known DRC Violations from Layout IP
Coaxial Measurements – Common Mistakes & Simple Solutions Sathya Padmanabhan Rocky Teresa Maury Microwave Corp. For electronic copy of presentation go.
Getting Started with Layout Compiled by Ryan Johnson May 1, 2002  Open Orcad Capture under Engineering Software  Under FILE, choose NEW, PROJECT  The.
QA/QC: A Checklist for Quality and Control
S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 24: Computer-Aided Design using Tanner Tools Prof. Sherief Reda Division.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 30: Design Methodologies using Tanner Tools Prof. Sherief Reda Division.
VLSI drawings transferring limitations (AKA ‘conversion problem’)
Command Interpreter Window (CIW)
Chonnam national university VLSI Lab 8.4 Block Integration for Hard Macros The process of integrating the subblocks into the macro.
EKT 221/4 DIGITAL ELECTRONICS II  Registers, Micro-operations and Implementations - Part3.
Synopsys Custom Designer Tutorial for a chip integration using the University of Utah Standard Cell Libraries In ON Semiconductor 0.5u C5 CMOS Version.
Slide 1 6. VHDL/Verilog Behavioral Description. Slide 2 Verilog for Synthesis: Behavioral description Instead of instantiating components, describe them.
Synopsys Custom Designer Tutorial for a chip integration using the University of Utah Standard Cell Libraries In ON Semiconductor 0.5u C5 CMOS Version.
Database Security Outline.. Introduction Security requirement Reliability and Integrity Sensitive data Inference Multilevel databases Multilevel security.
QA and Testing. QA Activity Processes monitoring Standards compliance monitoring Software testing Infrastructure testing Documentation testing Usability.
CADENCE CONFIDENTIAL 1CADENCE DESIGN SYSTEMS, INC. Cadence Front to Back End Adil Sarwar March 2004.
Version RAILER SMS RAILER RED (Remote Entry Database)
Registers; State Machines Analysis Section 7-1 Section 5-4.
UNIT 3 – MODULE 5: Data Input & Editing. INTRODUCTION Putting data into a computer (called data coding) is a fundamental process for virtually all GIS.
1 EE 382M VLSI 1 EE 360R Computer-Aided Integrated Circuit Design Lab 1 Demo Fall 2011 Whitney J. Wadlow.
Author 1 | Author 2 | Author 3 (edit this list via View > Slide Master) Two spaces should be between the line and the next author’s name Insert your unit.
 Pearson Education, Inc. All rights reserved Methods: A Deeper Look.
T3/Tutorials: Data Submission
Jim Fawcett CSE687-OnLine – Object Oriented Design Summer 2017
Design and Documentation
Advanced Programing practices
User-Written Functions
Physical Design of FabScalar Generated Cores
Library Characterization
CSC201: Computer Programming
Jim Fawcett CSE687 – Object Oriented Design Spring 2015
Data-Basics Training & Support
Digital Design Jeff Kautzer Univ Wis Milw.
Jody Matos, Augusto Neutzling, Renato Ribas and Andre Reis
Written by Whitney J. Wadlow
C++ Standard Library.
Error Correcting Code.
Top-level Schematics Digital Block Sign-off Digital Model of Chip
Dr Stephen Bell Rutherford Appleton Laboratory 18/12/2013
CPE/EE 428/528 VLSI Design II – Intro to Testing (Part 3)
Un</br>able’s MySecretSecrets
Lab1 Instruction Georeferencing a raster
FreePDK45nm Library Validation
Engineering notebook.
Degree works plans training
Programming in C Input / Output.
Data Link Layer: Data Link Control
*Includes adding a 658 Tag*
Timing Analysis 11/21/2018.
45nm example2 library Validation With Crossfire™
Importing Data from Excel (XLS) into P6 Client
The Updated Jordan-Falls Stormwater Nutrient Accounting Tool
Example of User Specific Scripts
Error Detection / Correction
ECE 352 Digital System Fundamentals
Psych 231: Research Methods in Psychology
Submitted by HARSHITHA G H
Verification and Validation
Comparison of table-based and JSON-based chaincode
EE382M VLSI 1 LAB 1 DEMO FALL 2018.
Running a Java Program using Blue Jay.
The MPAS project Multi-agent Pathfinding Algorithms Simulator
HIBBs is a program of the Global Health Informatics Partnership Learning the Basics of Microsoft Word 2019 and Microsoft office support TFN
Colorado PSAT/SAT SBD Training
SPL – PS1 Introduction to C++.
Chapter 3 Solid-State Diodes and Diode Circuits
Presentation transcript:

Typical STD Cell Library Errors Fractal Technologies Typical STD Cell Library Errors 1/11/2019 Fractal Technologies Confidential

Typical Cell Presence Errors Obsolete Cells Cadence DFII has many times hierarchical cells that are not used anymore. (Artefacts) Double cell entries Cells removed from Cadence DB still remain in other formats. (Verilog, MilkyWay, Liberty, etc...) Missing Cells Wrong database in cds.lib included. Hierarchical cells are missing. Cells in the CDB do not exist in the other formats due to later added cells not all Databases are updated or an older database is delivered Documentation many times misses a cell Due to no formal checking method Filler and alignment cells not consistent for the various DB’s 1/11/2019 Quality in Design Formats

Typical Terminals & Pins Errors Direction of the pins does not match Input,Output, Bidirectional Pins are in the wrong layer Uses busses instead of single pins 1/11/2019 Quality in Design Formats

Quality in Design Formats Typical Label Errors Missing labels Simply missing Typing errors Uppor vs lower case errors Labels in the wrong layer 1/11/2019 Quality in Design Formats

Quality in Design Formats Typical Net Errors Missing net information Due to copy actions in the Cadence Database Net information may be lost. Database corrupt… Busses used instead of single pins 1/11/2019 Quality in Design Formats

Typical Layout vs. layout Errors Modifications in the master Cadence Database not copied to GDSII or LEF 45 degrees not accurately enough in LEF Abstract not generated correctly Shifted polygons  1/11/2019 Quality in Design Formats

Typical Abutment Errors 1 grid shift  Missing boundary layer Layers do not touch the outline 1/11/2019 Quality in Design Formats

Typical Routability Errors Pins not on grid Wrongly coded off-set 1/11/2019 Quality in Design Formats

Typical Functional Equivalence Errors Both active PRESET and SET yield different result over the various formats Priority definitions wrong Mismatch between asynchronous and synchronous descriptions Missing functional description Short circuit detection Cont… 1/11/2019 Quality in Design Formats

Typical Functional Equivalence Errors Documentation errors Due to missing formal checking. (Depends on human reading) pin(OA1) { direction : output ; function : "(!M2|(M1&M0))" ; pin(OA2) { direction : output ; function : "(M2|(!M1&!M0))" ; pin(Z) { direction : output ; function : "!(M1^M0)" ; .lib  Datasheet  1/11/2019 Quality in Design Formats

Typical Characterization Errors Last characterization entries all 0. Delay decreases with increasing output load Conditional vs non-conditional descriptions Back-annotation errors Conditions don’t match string based Obsolete default conditions Non-paired setup and hold times Swapping of Liberty file names ff, tt, vs ss 1/11/2019 Quality in Design Formats

Typical CCS Characterization Errors Cells do not have a single peak current Current curves have a “correction current” at the tail 1/11/2019 Quality in Design Formats

Typical ECSM Characterization Errors ECSM-curves have large deviations (20-300%) between ECSM and NLDM delay values 1/11/2019 Quality in Design Formats

Quality in Design Formats Conclusions It’s better to check the STD Cell Library before using it 1/11/2019 Quality in Design Formats