D Flip-Flop Schematic Block Symbol Truth Table D Q Clk Q Clk D Q(t+1) X Q(t) 1 Clk Q

JK Flip-Flop J Q K Q Clk Truth Table Clk J K Q(t+1) X Q(t) 1 Q(t)’ X Q(t) 1 Q(t)’ Block Symbol JK FF Function: Adding inverter functionality to DFF J Q K Q Clk

T Flip-Flop Q Clk Q Truth Table Clk T Q(t+1) X Q(t) 1 Q(t)’ X Q(t) 1 Q(t)’ Block Symbol T FF Aplikasi : untuk menentukan bit pariti data serial T Q Clk Q

Finite State Machine Instructor : Nyoman Karna Course Number : FEH2H3 As Taught In : 1st semester 2017-2018 Level : Undergraduate

FSM Model Characteristics: FSM has the ability to memorize state

FSM Model MEALY: FSM model where the output state depends with input and present state. MOORE: Simplification from Mealy model where output state depends only with present state.

Mealy Model NS: Next State PS: Present State

Moore Model NS: Next State PS: Present State

Sequence of States

Number of States How many states does an FSM have? If an FSM has N variable state, then there will be a maximum of 2N states and a minimum of 2 states: 2 < (number of states) < 2N

State Diagram (1)

State Diagram (2) Simple 2-way state diagram using X as an input of the FSM. Move to the right when X (X=1) and to the left whenX (X=0)

State Diagram (3) Simple 2-way state diagram using X as an input of the FSM. Move to the right when X (X=1) and to the left whenX (X=0). The FSM has Z as the output of the FSM, become active (Z=1) when the 111 state is achieved (A = 1, B = 1, C = 1) Moore Model.

State Diagram (4) Simple 2-way state diagram using X as an input of the FSM. Move to the right when X (X=1) and to the left whenX (X=0). The FSM has Z as the output of the FSM, become active (Z=1) when the 111 state is achieved (A = 1, B = 1, C = 1) and X=1 Mealy Model.

State Diagram Creation: Rule #1 The sum (OR function) of all outgoing variable from every state = 1 Only 1 change in variable state (no 111  000)

Designing an FSM

FSM Synthesizing(1) 1. Identify the Flip-Flop Qt  Qt+1 S R 0  0 0  0 0  1 1  0 1  1 0  1 0 0 1  0 Qt  Qt+1 D 0  0 0  1 1  0 1  1 1 SET 1 SET HOLD Qt  Qt+1 T 0  0 0  1 1  0 1  1 0 RST HOLD 1 TOGGLE 0 SET HOLD Qt  Qt+1 J K 0  0 0  1 1  0 1  1 0  1   1  0

FSM Synthesizing (2) 2. Design a combinational logic to map the output - Moore: input = PS (Present State) - Mealy: input = PS (Present State) + FSM INPUT

FSM Synthesizing (3) 3. Design a combinational logic to map the NS (Next State) - Moore: - Mealy:

How many inputs does the FSM have? How many output does the FSM have? Example 1 How many inputs does the FSM have? How many output does the FSM have? How many FF does the FSM have? Which FF do we use? Create the logic to create output Create the logic to create NS A X B A 1 Z B

How many inputs does the FSM have? How many output does the FSM have? Practice 1 How many inputs does the FSM have? How many output does the FSM have? How many FF does the FSM have? Which FF do we use? Create the logic to create output Create the logic to create NS X 1

How many inputs does the FSM have? How many output does the FSM have? Practice 2 How many inputs does the FSM have? How many output does the FSM have? How many FF does the FSM have? Which FF do we use? Create the logic to create output Create the logic to create NS A X A A 1 A

How many inputs does the FSM have? How many output does the FSM have? Practice 3 How many inputs does the FSM have? How many output does the FSM have? How many FF does the FSM have? Which FF do we use? Create the logic to create output Create the logic to create NS A X B A 1 Z B

Practice 4 A A X 00 01 Z 10 11 B B

Practice 5 A A 00 01 Z 11 A A

Practice 6 A A 00 Z 11 A A