Chip Layout 27 F2 50 F2 35 F2 LUT 27 F2 50 F2 35 F2 27 F2 50 F2 35 F2 CHIP_TOP 27 F2 50 F2 35 F2 LUT CHIP_MIDDLE 27 F2 50 F2 35 F2 50 F2 Sharing CHIP_BOTTOM 27 F2 50 F2 35 F2 35 F2 Sharing

Memory Block Layout R MTJ MUX Read/Write Decoder Data SC Config RD SC PG MTJ: 2x 8Kbit Memory Array (27.75F2, 35F2, 50F2, 35F2 Sharing, 50F2 Sharing) MUX: 8-to-1 MUXs READ/WRITE: Read & Write Circuitry R: Resistor array for testing Read Delay circuit, parasitic resistance from access transistor, and transistor drive strength. Decoder: Row decoder. Data SC: Scan Chain to read data serially in and out of memory array Config SC: Scan Chain to configure the various testing modes & calibrate delay measurements RD: Read Delay Circuit PG: Write Pulse Generator