Getting Started with Baseline Architecture and Peripherals in Assembly V3.0 July 2015 Getting Started with Baseline Architecture and Peripherals in Assembly MCU0101

At the end of today you should be able to: Course Objectives At the end of today you should be able to: Understand the Architecture of the Baseline PIC Microcontroller Know how to program the peripherals on the baseline family Be able to write and debug programs that utilize the baseline architecture and peripherals

Introduction to the Baseline PIC Microcontroller Architecture Course Agenda Introduction to the Baseline PIC Microcontroller Architecture Special Features Baseline Family Peripherals Input/Output Port Timer 0 Analog-to-Digital Converter Comparator Hands-on Labs implementing each peripheral

Labs After Class Lab1 My first PIC project Complete lab manual and solutions are included in the student download materials. Lab1 My first PIC project Lab2 Introduction to the Baseline Instruction Set using MPLAB SIM Lab3 Addressing Data Memory Lab4 Addressing Program Memory Lab5 Working with I/O Ports Lab6 Using Timer0 to Create a Software Delay Lab7 Working with the ADC

Microchip Forums www.microchip.com Post your Lab questions Moderated by our instructors Search for previously answered questions Available 24 hours a day Doing the labs outside of class will allow you to complete them at your leisure. BUT you will not be on your own. Our training forums allow you to post home work question for our instructors at any time. While we can not monitor them 24/ 7, all our instructors monitor the forums and will help you through any difficulties.

Microchip Forums www.microchip.com Just go to Microchip.com and on the main page in the right hand column are the forums <click> This will take you directly to the main Microchip forum page. Here you can either search for your topic or scroll down near the bottom of the list to find the Training forums. There is a separate forum for each class. <click> In each forum you will find questions and answers of previous students and you can post your questions.

Microchip Developer Help www.microchip.com/developerhelp Google Searchable Thousands of topics New material added every week! Or through our main website under training

Introduction to Baseline PIC Microcontrollers

Baseline PIC Microcontroller Overview PROGRAM MEMORY Engine Runs the Microcontroller DATA MEMORY Oscillator Non-Volatile Volatile Holds program instructions to tell CPU what to do CPU Working STATUS OPTION Holds data under the control of the instructions Today we will be looking at the Baseline microcontroller. As was mentioned the CPU is the brains of the operation. Here all instruction, logic and mathematical operations are processed. Next, the oscillator. This will act as the engine for the microcontroller. A car can have a lot of features but they don’t do you much good if there is no engine. Program Memory is used to hold the instruction that will tell the CPU how to think. This is the code that you have written to define the application at hand. Data Memory will store data under the control of the instruction for use by the CPU. Important to note is that Program Memory is non-volatile. This means that even if you were to remove power and physically take the microcontroller out of the circuit, the code that you have programmed onto it will still exist the next time this device is powered up. Data Memory on the other hand is volatile. Removing power from the microcontroller will erase any values that were stored here. The Brains Performs all instruction, logic, and mathematical processing

Program Memory

Flash Program Memory Organization Stores the instructions from your code Tells the CPU what to do PIC Instruction Set operations are all 12-bits wide 1 instruction = 1 Program Memory Address Divided into pages The amount of Program Memory is device specific 12-BITS WIDE As was mentioned previously, Program Memory will contain the instructions that will tell the CPU what to do. On the Baseline Microcontrollers, Program Memory is made up of 12-bit registers. These registers will each reside at their own individual address location. Program Memory is further grouped into Pages each containing 512 12-bit address locations. Just as with Data Memory, the amount of Program Memory you have on a specific device will vary.

Flash Program Memory Organization Stores the instructions from your code Tells the CPU what to do PIC Instruction Set operations are all 12-bits wide 1 instruction = 1 Program Memory Address Divided into pages The amount of Program Memory is device specific Page 0 1024 x 12-bits As was mentioned previously, Program Memory will contain the instructions that will tell the CPU what to do. On the Baseline Microcontrollers, Program Memory is made up of 12-bit registers. These registers will each reside at their own individual address location. Program Memory is further grouped into Pages each containing 512 12-bit address locations. Just as with Data Memory, the amount of Program Memory you have on a specific device will vary. Page 1

Why Program Memory Paging With a 12 bit instruction at the most only 9 bits can be used to specify a program memory address GOTO Instruction in Program Memory 11 10 9 8 7 6 5 4 3 2 1 Opcode 1 29 = 512 = number of memory address accessed by a 9-bit operand Some programs need to address more than 512 separate program memory address !

Program Counter 1 1 1 1 1 1 1 1 1 1 1 1 10-bit PC 9 8 7 6 5 4 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 10-bit PC 210 = 1024 address locations Contains address of NEXT instruction Runs freely across page boundaries Events that modify PC out of sequence: Instructions: CALL, GOTO, RETLW Any instruction that uses the PCL register as an operand Program Memory PCL The Program Counter is a 10-bit register that stores the address of the next sequential instruction to be executed from Program Memory. Notice that the lower 8-bits (byte) of the PC can be accessed directly using the Program Counter Low (PCL) Special Function Register. We can modify the PC out of sequence by modifying the PCL register. Furthermore, issuing certain instructions such as CALL, GOTO and RETLW, will also modify the PC.

Program Page Selection using STATUS GPWUF CWUF PA0 TO PD Z DC C Program Memory PA0: Program Page Preselect bit PA0 = 1 Page 1(200h – 3FFh) PA0 = 0 Page 0(000h – 1FFh) PA0 = 0 PAGE0 The Program Page Preselect bit (STATUS<PA0>, as the name implies, is used to select a PAGE in program memory. The importance of this bit will become clear when we discuss branching instructions later in this class. PA0 = 1 PAGE1

How Paging is Implemented STATUS GOTO Instruction in Program Memory PA0 11 10 9 8 7 6 5 4 3 2 1 PA0 Opcode 1 9 8 7 6 5 4 3 2 1 1 Effective Address Program Counter

The STATUS Register

Status Register Rotate Right Rotate Left Contains: STATUS GPWUF CWUF PA0 TO PD Z DC C Zero bit (Z): result of arithmetic/logic operation is zero i.e. 1 – 1 = 0 (Z = 1) move zero value into a register (Z = 1) Contains: Arithmetic status bits The RESET status Program Memory Page Select Wake-up from SLEEP Flags Rotate Right Rotate Left C 1 1 1 1 The STATUS register contains information related to the status of the CPU. Information about arithmetic operations and device RESET sources will set or clear individual bits in this register. We will look more closely at the bits associated with RESETs later in this course. For now, the arithmetic status and Program Memory Page Select bits will be discussed. Three bits in the STATUS register STATUS<2:0> are used to communicate arithmetic status of a particular operation. The Z bit or Zero bit is used to indicate that an operation has resulted in a zero value. Arithmetic and logic operations resulting in a zero value will set this bit to 1. Another useful feature occurs when a zero value is moved into a register. If that value equates to zero, the zero bit will also set. The CARRY/BORROW bit is used in three ways: When adding two values together, this bit will set if the result exceeds an 8-bit value or 255 decimal. When subtracting two values, this bit will clear to zero if the result produces a negative value (i.e. a value is subtracted from a lesser value) The CARRY/BORROW bit also plays a role in bit rotation instructions. Rotating bits right as in the RRF instruction moves the STATUS<C> bit (whatever value it holds) into the MSb position in the file register being worked upon. The lsb from the file register is then moved into the STATUS<C> bit position. Each subsequent RRF instruction will move the next lsb into STATUS<C> bit location and so on. Arithmetic STATUS bits can become a powerful tool in conditional loops in your code. The Digit Carry bit is commonly used in NIBBLE binary arithmetic. This bit is not discussed here as it falls outside the intended scope of this course. For more information on the STATUS<DC> bit please refer to the datasheet. 1 C 1 C C 1 C 1 1 C 1 C 1 C 1 C 1 MSB LSB

Status Register Rotate Right Rotate Left Contains: STATUS GPWUF CWUF PA0 TO PD Z DC C Carry/borrow (C) Addition: Addition result exceeds 255 (28 – 1) 125 + 140 = 265 (C = 1) 125 + 125 = 250 (C = 0) Subtraction: Value is subtracted from a lesser value 125 - 140 = -15 (C = 0) 125 - 120 = 5 (C = 1) Contains: Arithmetic status bits The RESET status Program Memory Page Select Wake-up from SLEEP Flags Rotate Right Rotate Left C 1 1 1 1 The STATUS register contains information related to the status of the CPU. Information about arithmetic operations and device RESET sources will set or clear individual bits in this register. We will look more closely at the bits associated with RESETs later in this course. For now, the arithmetic status and Program Memory Page Select bits will be discussed. Three bits in the STATUS register STATUS<2:0> are used to communicate arithmetic status of a particular operation. The Z bit or Zero bit is used to indicate that an operation has resulted in a zero value. Arithmetic and logic operations resulting in a zero value will set this bit to 1. Another useful feature occurs when a zero value is moved into a register. If that value equates to zero, the zero bit will also set. The CARRY/BORROW bit is used in three ways: When adding two values together, this bit will set if the result exceeds an 8-bit value or 255 decimal. When subtracting two values, this bit will clear to zero if the result produces a negative value (i.e. a value is subtracted from a lesser value) The CARRY/BORROW bit also plays a role in bit rotation instructions. Rotating bits right as in the RRF instruction moves the STATUS<C> bit (whatever value it holds) into the MSb position in the file register being worked upon. The lsb from the file register is then moved into the STATUS<C> bit position. Each subsequent RRF instruction will move the next lsb into STATUS<C> bit location and so on. Arithmetic STATUS bits can become a powerful tool in conditional loops in your code. The Digit Carry bit is commonly used in NIBBLE binary arithmetic. This bit is not discussed here as it falls outside the intended scope of this course. For more information on the STATUS<DC> bit please refer to the datasheet. 1 C 1 C C 1 C 1 1 C 1 C 1 C 1 C 1 MSB LSB

Rotate Left or Right: Move C into msb or lsb of register Status Register STATUS GPWUF CWUF PA0 TO PD Z DC C Rotate Left or Right: Move C into msb or lsb of register Rotate Right 1 1 C 1 1 The STATUS register contains information related to the status of the CPU. Information about arithmetic operations and device RESET sources will set or clear individual bits in this register. We will look more closely at the bits associated with RESETs later in this course. For now, the arithmetic status and Program Memory Page Select bits will be discussed. Three bits in the STATUS register STATUS<2:0> are used to communicate arithmetic status of a particular operation. The Z bit or Zero bit is used to indicate that an operation has resulted in a zero value. Arithmetic and logic operations resulting in a zero value will set this bit to 1. Another useful feature occurs when a zero value is moved into a register. If that value equates to zero, the zero bit will also set. The CARRY/BORROW bit is used in three ways: When adding two values together, this bit will set if the result exceeds an 8-bit value or 255 decimal. When subtracting two values, this bit will clear to zero if the result produces a negative value (i.e. a value is subtracted from a lesser value) The CARRY/BORROW bit also plays a role in bit rotation instructions. Rotating bits right as in the RRF instruction moves the STATUS<C> bit (whatever value it holds) into the MSb position in the file register being worked upon. The lsb from the file register is then moved into the STATUS<C> bit position. Each subsequent RRF instruction will move the next lsb into STATUS<C> bit location and so on. Arithmetic STATUS bits can become a powerful tool in conditional loops in your code. The Digit Carry bit is commonly used in NIBBLE binary arithmetic. This bit is not discussed here as it falls outside the intended scope of this course. For more information on the STATUS<DC> bit please refer to the datasheet. 1 C 1 C C 1 1 1 1 C 1 C 1 C 1 C MSB LSB

Rotate Left or Right: Move C into msb or lsb of register Status Register STATUS GPWUF CWUF PA0 TO PD Z DC C Rotate Left or Right: Move C into msb or lsb of register Rotate Left 1 1 C 1 1 The STATUS register contains information related to the status of the CPU. Information about arithmetic operations and device RESET sources will set or clear individual bits in this register. We will look more closely at the bits associated with RESETs later in this course. For now, the arithmetic status and Program Memory Page Select bits will be discussed. Three bits in the STATUS register STATUS<2:0> are used to communicate arithmetic status of a particular operation. The Z bit or Zero bit is used to indicate that an operation has resulted in a zero value. Arithmetic and logic operations resulting in a zero value will set this bit to 1. Another useful feature occurs when a zero value is moved into a register. If that value equates to zero, the zero bit will also set. The CARRY/BORROW bit is used in three ways: When adding two values together, this bit will set if the result exceeds an 8-bit value or 255 decimal. When subtracting two values, this bit will clear to zero if the result produces a negative value (i.e. a value is subtracted from a lesser value) The CARRY/BORROW bit also plays a role in bit rotation instructions. Rotating bits right as in the RRF instruction moves the STATUS<C> bit (whatever value it holds) into the MSb position in the file register being worked upon. The lsb from the file register is then moved into the STATUS<C> bit position. Each subsequent RRF instruction will move the next lsb into STATUS<C> bit location and so on. Arithmetic STATUS bits can become a powerful tool in conditional loops in your code. The Digit Carry bit is commonly used in NIBBLE binary arithmetic. This bit is not discussed here as it falls outside the intended scope of this course. For more information on the STATUS<DC> bit please refer to the datasheet. 1 C 1 C C 1 1 1 1 C 1 C 1 C 1 C MSB LSB

Data Memory

Data Memory Organization Grouped into BANKs Contains Special Function Registers (SFR) General Purpose Registers (GPR) BANK of Data Memory 8-bits Wide SFR Data Memory on the Baseline PIC Microcontroller is made up of 8-bit registers. Each one of these 8-bit registers have their own specific address location. Data memory registers are grouped in blocks called BANKS.These 8-bit registers are collectively store in blocks called banks. There are two types of data memory: Special Function Registers and General Purpose registers. GPR

Special Function Registers PIC12F510 Data Memory SFRs INDF TMR0 PCL STATUS FSR OSCCAL GPIO CM1CON0 ADCON0 ADRES Control CPU and Peripheral functions Control the operation of the device SFR addresses are fixed Number of SFRs is device specific 00 01 02 03 04 05 06 07 Special Function Registers control the operation of the device. These registers will perform a specific function and are therefore not addressable. Setting (=1) or Clearing (=0) a bit in one of these registers will directly have an impact on either the CPU or one of the Peripherals. Highlighted in purple in the slide above are the SFRs specific to one of the peripherals we will learn about in this course. Manipulating one of the 8 bits in each of these registers will cause the associated peripheral to behave differently. These registers are typically defined in a .inc file that is available for use within the MPLAB Integrated Development Environment we will use to write our code today. Again, depending on the particular member of the Baseline family, the number of SFRs will differ. 08 09

General Purpose Registers BANK of Data Memory Store Data Control information under command of the instructions Stores user defined variables Selectable address Number of GPRs is device specific SFRs General Purpose registers are were user defined data is stored under the control of the instructions. Variables that you create to be used in your code is stored in this area of Data Memory. The user also has control of where exactly these variables are located. Depending on the specific Baseline Family member you are using the number of GPR Data Memory at your disposal will vary. GPR

Data Memory Organization PIC12F510 Some data memory registers are accessible from any BANK Others are not PIC12F510 Data Memory is shown Number of BANKS and register accessibility varies with device Bank 0 Bank 1 00 20 INDF INDF TMR0 PCL STATUS FSR OSCCAL GPIO CM1CON0 ADCON0 ADRES GPR1 GPR2 GPR3 GPR4 GPR5 GPR6 INDF 01 TMR0 21 TMR0 02 PCL PCL 22 03 23 STATUS STATUS 04 FSR FSR 24 05 25 OSCCAL OSCCAL 06 26 GPIO GPIO 07 CM1CON0 27 CM1CON0 08 ADCON0 ADCON0 28 09 29 ADRES ADRES 0A 2A GPR1 GPR1 0B 2B GPR2 GPR2 0C GPR3 GPR3 2C This is a view of the low addresses of the two banks, showing the SFRs. Note that on this particular microcontroller (PIC12F510) all of the SFRs and some of the GPRs are accessible from any bank. As we look a little closer at accessing individual data memory location you will realize that depending on the specific bank you are in will determine whether or not some of the registers can be written or read from. 0D 2D GPR4 GPR4 0E 2E GPR5 GPR5 0F GPR6 2F GPR6 GPRs after addresses 0Fh and 2Fh can only be accessed if CPU is set to that BANK (PIC12F510) 10 30 11 31 12 32 13 33 14 34

Why Data Banking OPCODE OPCODE d OPERAND 12 6 5 4 0 Baseline PIC instructions have only 5 bits to describe an for the destination of an instructions ( OPERAND) 25 = 32 unique destination addresses ! Many Baseline PIC applications require more than 32 data memory locations !

How Data Banking is Implemented Banking “extends” the address range of the MCU by combining the instruction OPERAND with two bits in the FSR register 12-bit Instruction opcode FSR register 1 1 1 1 1 1 BANK select bits OPERAND 27 bits = 128 unique memory addresses

What Data Memory “looks” like 09 0A 10 1F BANK 0 BANK 1 BANK2 BANK 3 FSR Bank Select Bits x x

The Baseline Instruction Set

Baseline Instruction Set Byte Oriented Operations Bit Oriented Operations addwf f,d Add W and f bcf f,b Bit Clear f andwf f,d AND W with f bsf f,b Bit Set f clrf f Clear f btfsc f,b Bit Test f, Skip if Clear clrw - Clear W btfss f,b Bit Test f, Skip if Set comf f,d Complement f Literal and Control Operations decf f,d Decrement f andlw k AND literal with W decfsz f,d Decrement f, Skip if 0 call k Call subroutine incf f,d Increment f clrwdt - Clear Watchdog Timer incfsz f,d Increment f, Skip if 0 goto k Go to address iorwf f,d Inclusive OR W with f iorlw k Inclusive OR literal with W movf f,d Move f The 33 Baseline Instructions are used to develop the application code or firmware that will be stored in Program Memory. As we will see, each instruction is only 12-bits wide meaning that each 12-bit Program Memory address can accommodate and entire single instruction. The Baseline Instruction Set is grouped into three categories: Byte-oriented operations, bit-oriented operations and Literal/control operations. movlw k Move literal to W movwf f Move W to f option - Load OPTION Register nop - No Operation retlw k Return with literal in W rlf f,d Rotate Left f through Carry sleep - Go into standby mode rrf f,d Rotate Right f through Carry tris f Load TRIS Register subwf f,d Subtract W from f xorlw k Exclusive OR literal with W swapf f,d Swap nibbles in f xorwf f,d Exclusive OR W with f

The Working Register The 8-bit Working Register: Two-operand instructions one operand is typically the W (working) register other operand is either a file register (in Data Memory) or immediate constant Single-operand instructions the operand is either the W register or a file register Move a value into a Data Memory file register Move a value from one Data Memory file register to another In order to effectively use the Baseline Instruction Set, a very important register needs to be discussed. The working register is the “work horse” of the entire system. Many of the operations will require that the Working Register is used such as: Anytime two bytes are being added together or used in a logic operation, one byte must come from the working register. So all Add, subtract and logic operations are designed to add the byte in the W register to a file register. To move data around in Data Memory (i.e. from one register to another) the Working register will need to be used as a transition location. Data cannot be moved from one Data Memory address to another without using the working register.

Byte-Oriented Operations Operate on the entire register/byte Arithmetic operations (ADDWF, SUBWF…) Logic operations (ANDWF, XORWF, COMF…) Shift operations (RRF, RLF) Data moving (MOVF, MOVWF, SWAPF…) Branching operations (INCFSZ, DECFSZ) OPCODE d File Register Address addwf GPIO, F Byte oriented operations, as the name implies, will work on the entire 8-bits in a given Data Memory address location. Arithmetic, logic, rotate, data moving and branching operations can all be done using byte-oriented operations. Remember, each program memory location is 12 bits wide. Note byte-oriented instructions (as all Baseline instructions) are all 12-bits wide. This essentially means that any one of the Baseline Instructions and their operands will occupy only one Program Memory Address location. You could basically count the lines in your code and be able to deduce the amount of Program Memory being used. Each category of instruction will be constructed differently. As shown in the slide above, the byte-oriented instruction will have 6 bits dedicated to the OPCODE (bit sequence that the CPU identifies as a specific command), 1 bit dedicated to the destination (where a result is to be stored) and 5 bits dedicated to hold the address location in Data Memory that a specific register to be acted upon resides. 1 1 1 d = 0 for destination W d = 1 for destination f file at address 0x06h (01102) operation destination

Bit-Oriented Operations Single bit manipulation (BSF, BCF) Single bit tests (BTFSS, BTFSC) OPCODE Bit Number File Register Address bcf GPIO, 3 Bit-oriented operations will act on a single bit only in a given register. Note how the 12-bit instruction has changed. Now only 4 bits are dedicated to the OPCODE, 3 bits are now needed to identify a specific bit position, and 5 bits are still used to identify the register to be acted upon’s Data Memory address. 1 1 1 file at address 0x06h (01102) operation Bit Number

Literal and Control Operations Literal instructions: Employ user defined values Logic operations (ANDLW, XORLW…) OPCODE Literal Value movlw 0xFF 1 1 The final category of instructions can be subdivided into two types: Literal Instructions are used to specifically define a value in the user’s code to be used in a mathematical or logic operation. Note that the 12-bit instruction now only has 4 bits for the OPCODE leaving 8 bits to identify an 8-bit literal value. Remember, data memory is 8 bits wide. Control Operations will control certain functional characteristics. For example, the SLEEP command will place the Microcontroller into a low-power mode, the CLRWDT (Clear Watchdog Timer) will clear the WDT register. There are also some commands that relate directly to Program Execution flow. The GOTO instruction for example will tell the CPU to JUMP to a different area of Program Memory and begin executing code there. As a result, the 12-bits for the GOTO instruction will need to accommodate this function. As shown above, a 3 bit OPCODE identifies the GOTO instruction to the CPU. The CPU now needs to know where exactly in Program Memory it needs to go to. A 9-bit value is therefore provided in the instruction to identify one of 512 address location on a given page in Program Memory. operation Literal value (11111112)

Literal and Control Operations Literal instructions: Employ user defined values Logic operations (ANDLW, XORLW…) Control instructions: SLEEP, CLRWDT, GOTO, CALL, RETLW The final category of instructions can be subdivided into two types: Literal Instructions are used to specifically define a value in the user’s code to be used in a mathematical or logic operation. Note that the 12-bit instruction now only has 4 bits for the OPCODE leaving 8 bits to identify an 8-bit literal value. Remember, data memory is 8 bits wide. Control Operations will control certain functional characteristics. For example, the SLEEP command will place the Microcontroller into a low-power mode, the CLRWDT (Clear Watchdog Timer) will clear the WDT register. There are also some commands that relate directly to Program Execution flow. The GOTO instruction for example will tell the CPU to JUMP to a different area of Program Memory and begin executing code there. As a result, the 12-bits for the GOTO instruction will need to accommodate this function. As shown above, a 3 bit OPCODE identifies the GOTO instruction to the CPU. The CPU now needs to know where exactly in Program Memory it needs to go to. A 9-bit value is therefore provided in the instruction to identify one of 512 address location on a given page in Program Memory. OPCODE Program Memory Address goto Function 1 1 Paging bit comes from STATUS operation Address in Memory

Addressing Modes

Addressing Modes Data Memory Access: Directly from the Program Memory Instruction example: clrf <data address> Indirectly using the File Select Register (FSR) as a pointer movlw <data address> movwf FSR ;Point to <data address> clrf INDF ;Clear <data address> ;pointed to by FSR There are two ways in which we can access a specific address in Data Memory: The first method we have already seen. The instruction from Program Memory will identify which address in Data Memory our operation is to affect. Indirect addressing is an alternate method to address Data Memory. To accomplish this method, two Special Function registers are needed. The File Select Register (FSR) is used to hold the address value in Data Memory for the register that will be modified. The Indirect File Register (INDF) will be needed then to modify the register pointed to by the FSR.

Addressing Modes Direct Addressing: 1 1 1 1 1 1 1 1 BANK is selected using FSR<5> Data Memory Address included in the instruction from Program Memory 12-bit Instruction opcode File Select Register (FSR) 1 1 1 1 1 1 1 1 Location select BANK select 00 Looking a little more closely at Direct Addressing, we see that the specific address in Data Memory is actually part of our 12-bit instruction. The File Select Register is used to select one of the banks in which our register resides. As we mentioned earlier, some of the registers are not shared across banks. Therefore, depending on which bank the register you wish to modify resides, the FSR Bank Select bit will need to be set or cleared accordingly. 0F 10 BANK0 BANK1

Addressing Modes Direct Addressing: Indirect Addressing: 1 1 1 1 1 1 1 Data Memory Address included in the instruction from Program Memory BANK is selected using FSR<5> Indirect Addressing: Data Memory Address is written into the File Select Register (FSR) Address is access via INDF register File Select Register (FSR) 1 1 1 1 1 1 1 1 BANK select Location select 00 When using Indirect Addressing, the address in Data Memory for a particular register now comes from the FSR register. Banking is still accomplished using the Bank Select bit. 0F 10 BANK0 BANK1

Instruction Pipelining Oscillator is internally divided by four Instruction cycle (TCY) = FOSC/4 = TOSC x 4 Fetching an instruction = 1 TCY Executing an instruction = 1 TCY Pipelining = simultaneous Fetch/Execute Fetch/Execute = 1TCY Program Branches = 2 TCY The oscillator frequency on the PIC Microcontroller is divided by 4 to produce what’s called an instruction clock cycle (TCY). Most instructions contained in Program Memory will take 1 TCY to execute. Furthermore, since Program and Data Memory are separate, the PIC Microcontroller implements a technique known as pipelining. What this means is that an instruction can be executed while fetching the next instruction. This will all take place in one TCY. However, any instruction that modifies the Program Counter such as program branches (GOTO, CALL, RETLW) will take two TCY. Since the PC holds the next sequential address, a FLUSH will need to occur to remove this address value and load the new address location where the PC is to JUMP to.

Instruction Pipelining MAIN MOVLW 0x03 ;move 0x03 (00000011) into Wreg MOVWF GPIO ;move value in Wreg into GPIO GOTO Label_1 ;Jump to Program Memory called Label_1 BSF GPIO, 1 Label_1 ;Code elsewhere in memory <code> TOSC TCY1 TCY2 TCY3 TCY4 TCY5 TCY6 The oscillator frequency on the PIC Microcontroller is divided by 4 to produce what’s called an instruction clock cycle (TCY). Most instructions contained in Program Memory will take 1 TCY to execute. Furthermore, since Program and Data Memory are separate, the PIC Microcontroller implements a technique known as pipelining. What this means is that an instruction can be executed while fetching the next instruction. This will all take place in one TCY. However, any instruction that modifies the Program Counter such as program branches (GOTO, CALL, RETLW) will take two TCY. Since the PC holds the next sequential address, a FLUSH will need to occur to remove this address value and load the new address location where the PC is to JUMP to. FETCH MOVLW 0x03 EXECUTE MOVLW 0x03 FETCH MOVWF GPIO EXECUTE MOVWF GPIO FETCH GOTO SUB_1 EXECUTE GOTO SUB_1 FETCH BSF GPIO,1 FLUSH BSF GPIO,1 FETCH Label_1 EXECUTE Label_1

9-bits from instruction GOTO Instruction STATUS GOTO Instruction in Program Memory 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 PA0 Opcode 1 9 8 7 6 5 4 3 2 1 10-Bit Program Counter 1 1-bit from STATUS Determines Page 9-bits from instruction 29 = 512 Address Locations The first program branch instruction is the GOTO instruction. Remember that the 12-bit GOTO instruction will contain a 9-bit address value that the PC is to jump to. Since 29 = 512, only 512 address locations can be accessed using a GOTO. However, on the PIC12F510 there are 1024 possible address locations. As was mentioned previously, the Program Memory is divided into Pages each containing 512 12-bit address locations. Note in the slide above that an additional bit is added to PC<9>. This is the page pre-select bit that was discussed back in the STATUS register. By either setting or clearing this bit we have selected one of the Pages and when combined with the 9-bit address value from the instruction allows access to all Program Memory address locations. In order to return to where program execution was prior to the GOTO another GOTO will be required.

The CALL and RETLW Instruction STATUS CALL Instruction in Program Memory 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 PA0 Opcode 1 8-bits from instruction 28 = 256 Address Locations PA0 from STATUS Determines Page 9 8 7 6 5 4 3 2 1 10-Bit Program Counter 1 Only the first 256 addresses on a given page can be accessed using a CALL Always cleared with the execution of CALL The CALL and RETLW can be used to execute a subroutine located elsewhere in program memory and return to where program execution was prior to the jump after this subroutine has been executed. To accomplish this, the PC will need to temporarily store its contents so that it knows where to return to following the execution of the subroutine. The PC value is temporarily stored onto a 2-level STACK. When a CALL instruction is executed the contents of the PC are PUSHED onto the top-level of this STACK. Once the subroutine is finished executing, the top level of the STACK is reloaded or POPed back into the PC using the RETLW instruction and program execution can continue from where it left off prior to the CALL. It is important to remember that the RETLW will load a value into the Working Register. Therefore, if the contents of the WREG need to be preserved, they will need to be stored temporarily elsewhere. As with the GOTO statement the STATUS<PA0> bit is used to select the PAGE that our subroutine will reside in. However, the main difference between the CALL and GOTO is that only 8-bits in the CALL instruction are provided to the PC for the Program Memory Address. Also, note that the PC<8> bit is cleared during the execution of a CALL. This means that the CALL instruction can only be used to access the first 28 = 256 Program Memory address locations on a given page. Since the STACK is only 2 levels deep, performing more than two subsequent CALLS will result in the PC address located on the second level to lost. 2 Level STACK

The CALL and RETLW Instruction STATUS CALL Instruction in Program Memory 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 PA0 Opcode 1 8-bits from instruction 28 = 256 Address Locations PA0 from STATUS Determines Page 9 8 7 6 5 4 3 2 1 10-Bit Program Counter CALL PUSHes STACK PC value moved onto top level Clears bit 8 of the PC 1 PUSH Always cleared with the execution of CALL The CALL and RETLW can be used to execute a subroutine located elsewhere in program memory and return to where program execution was prior to the jump after this subroutine has been executed. To accomplish this, the PC will need to temporarily store its contents so that it knows where to return to following the execution of the subroutine. The PC value is temporarily stored onto a 2-level STACK. When a CALL instruction is executed the contents of the PC are PUSHED onto the top-level of this STACK. Once the subroutine is finished executing, the top level of the STACK is reloaded or POPed back into the PC using the RETLW instruction and program execution can continue from where it left off prior to the CALL. It is important to remember that the RETLW will load a value into the Working Register. Therefore, if the contents of the WREG need to be preserved, they will need to be stored temporarily elsewhere. As with the GOTO statement the STATUS<PA0> bit is used to select the PAGE that our subroutine will reside in. However, the main difference between the CALL and GOTO is that only 8-bits in the CALL instruction are provided to the PC for the Program Memory Address. Also, note that the PC<8> bit is cleared during the execution of a CALL. This means that the CALL instruction can only be used to access the first 28 = 256 Program Memory address locations on a given page. Since the STACK is only 2 levels deep, performing more than two subsequent CALLS will result in the PC address located on the second level to lost. 2 Level STACK

The CALL and RETLW Instruction STATUS CALL Instruction in Program Memory 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 PA0 Opcode 1 8-bits from instruction 28 = 256 Address Locations PA0 from STATUS Determines Page 9 8 7 6 5 4 3 2 1 10-Bit Program Counter CALL PUSHes STACK PC value moved onto top level Clears bit 8 of the PC RETLW POPs STACK top level moved into PC 1 POP Always cleared with the execution of CALL The CALL and RETLW can be used to execute a subroutine located elsewhere in program memory and return to where program execution was prior to the jump after this subroutine has been executed. To accomplish this, the PC will need to temporarily store its contents so that it knows where to return to following the execution of the subroutine. The PC value is temporarily stored onto a 2-level STACK. When a CALL instruction is executed the contents of the PC are PUSHED onto the top-level of this STACK. Once the subroutine is finished executing, the top level of the STACK is reloaded or POPed back into the PC using the RETLW instruction and program execution can continue from where it left off prior to the CALL. It is important to remember that the RETLW will load a value into the Working Register. Therefore, if the contents of the WREG need to be preserved, they will need to be stored temporarily elsewhere. As with the GOTO statement the STATUS<PA0> bit is used to select the PAGE that our subroutine will reside in. However, the main difference between the CALL and GOTO is that only 8-bits in the CALL instruction are provided to the PC for the Program Memory Address. Also, note that the PC<8> bit is cleared during the execution of a CALL. This means that the CALL instruction can only be used to access the first 28 = 256 Program Memory address locations on a given page. Since the STACK is only 2 levels deep, performing more than two subsequent CALLS will result in the PC address located on the second level to lost. 2 Level STACK

Special Features of the CPU

Oscillators

Oscillators on the PIC12F510 The PIC12F510 can operate in 4 different oscillator modes: LP: Low-Power Crystal (0 - 200kHz) XT: Crystal or Ceramic Resonator (0 - 4MHz) INTOSC: Internal 4/8MHz Oscillator EXTRC: External Resistor Capacitor (0 - 4MHz) FREQUENCY RANGE 0-8MHz ACCURACY High Medium Low COST Low Medium Zero Low Depending on the Baseline family you are using, a number of different oscillator modes are available. For example, the PIC12F510 can operate in any one of four different modes. Depending on the application at hand some decisions will need to be made about which oscillator to use. Does the application require a very accurate oscillator, what is the frequency range needed. Oscillator selections will also affect power consumption. Faster oscillators naturally will require more power to operate. Slower oscillators use less power and may be less expensive. Whatever oscillator you decide on, the PIC Microcontroller will need to be configured accordingly. Later in this section, configuration bits are discussed. Configuring the PIC to the appropriate oscillator will ensure that it operates effectively. LP 0 - 200 kHz XT 0 – 4 MHz INTOSC Up to 8 MHz RC Up to 8 MHz OSCILLATOR

Oscillators on the PIC12F510 FREQUENCY RANGE 0-8MHz ACCURACY High Medium Low COST Low Medium Zero Low Depending on the Baseline family you are using, a number of different oscillator modes are available. For example, the PIC12F510 can operate in any one of four different modes. Depending on the application at hand some decisions will need to be made about which oscillator to use. Does the application require a very accurate oscillator, what is the frequency range needed. Oscillator selections will also affect power consumption. Faster oscillators naturally will require more power to operate. Slower oscillators use less power and may be less expensive. Whatever oscillator you decide on, the PIC Microcontroller will need to be configured accordingly. Later in this section, configuration bits are discussed. Configuring the PIC to the appropriate oscillator will ensure that it operates effectively. LP 0 - 200 kHz XT 0 – 4 MHz INTOSC Up to 8 MHz RC Up to 8 MHz OSCILLATOR

Internal Oscillator Most Baseline devices contain a 4 and/or 8MHz internal oscillator Factory calibrated up to ± 1% Calibrated using the Oscillator Calibration (OSCCAL) SFR Oscillator specifications are Vdd and Temperature dependent The internal oscillator on the PIC12F510 can be configured to operate at 4 or 8MHz. Having an on-chip oscillator minimizes external components to the PIC thereby minimizing board real estate requirements.

Oscillator Calibration Register (OSCCAL) Calibrates internal oscillator precision Must be loaded upon any RESET The Oscillator Calibration Register allows the user to fine-tune the oscillator. Oscillator functionality will be susceptible to power supply voltages and temperature of the operating environment. Note that any changes to this register should only be performed by intermediate users. The beginner may want to avoid modify this registers contents until more experienced.

Oscillator Calibration Register (OSCCAL) bits 7-1 CAL<6:0> : Oscillator Calibration Bits 0111111 = Maximum Frequency . 0000000 = Center Frequency 1000000 = Minimum Frequency bit 0 Unimplemented: Read as ‘0’ Calibrates internal oscillator precision Must be loaded upon any RESET The Oscillator Calibration Register allows the user to fine-tune the oscillator. Oscillator functionality will be susceptible to power supply voltages and temperature of the operating environment. Note that any changes to this register should only be performed by intermediate users. The beginner may want to avoid modify this registers contents until more experienced.

Loading the OSCCAL Value RESET Vector Code execution begins here Holds the Oscillator Calibration bits OSCCAL is loaded at address 0000h User’s program starts executing at 0001h Program Memory 0000h 0001h 01FFh PAGE0 0200h PAGE1 All code that is written for the Baseline PIC Microcontroller should include a section that will load a factory calibrated OSCCAL value before the users application code. This factory calibrated value is physically located at address 03FFh in Program Memory. This particular address is known as the Reset Vector which means that anytime the PIC is RESET, the PC will point to this location and then begin code execution. The Baseline microcontroller has been designed so that the factory OSCCAL value will automatically load into the Working Register on any RESET. It is now the responsibility of the user to move the WREG value into OSCCAL using the MOVWF command. The code example shown above is included in all of the Baseline Family template files that comes with the MPLAB IDE. Once the OSCCAL value is loaded, the user’s application code can then begin. 03FFh movlw ‘OSCCALvalue’ RESET VECTOR

Loading the OSCCAL Value Working Factory cal. OSCAL value Program Memory 0000h movwf OSCCAL OSCAL 0001h User Code begins Factory cal. OSCAL value Loading the OSCCAL Value 01FFh PAGE0 ORG 0x3FF ;Internal RC calibration value is ;placed at location 0x3FF by Microchip ;as a movlw k, where the k is a ;literal value. ORG 0x000 movwf OSCCAL ;update register ;with factory ;cal value <Application Code> 0200h PAGE1 All code that is written for the Baseline PIC Microcontroller should include a section that will load a factory calibrated OSCCAL value before the users application code. This factory calibrated value is physically located at address 03FFh in Program Memory. This particular address is known as the Reset Vector which means that anytime the PIC is RESET, the PC will point to this location and then begin code execution. The Baseline microcontroller has been designed so that the factory OSCCAL value will automatically load into the Working Register on any RESET. It is now the responsibility of the user to move the WREG value into OSCCAL using the MOVWF command. The code example shown above is included in all of the Baseline Family template files that comes with the MPLAB IDE. Once the OSCCAL value is loaded, the user’s application code can then begin. 03FFh movlw ‘OSCCALvalue’ RESET VECTOR

Reset

SFRs are RESET (Check Datasheet) and GPR values are unknown. Baseline PIC Microcontroller begins program execution at the RESET Vector We looked at the RESET vector but what is a RESET? A RESET is an event that causes the Program Counter to return to the RESET Vector. The PIC12F510 differentiates between various RESETS. Upon any RESET the SFR registers in Data Memory will change to a RESET value as listed in the datasheet while GPR register values will be unknown.

PIC12F510 differentiates between various types of RESET: MCLR Reset (External) Power-on Reset (POR) WDT Time-out Reset Wake-up from SLEEP on pin change Wake-up from SLEEP on Comparator change We looked at the RESET vector but what is a RESET? A RESET is an event that causes the Program Counter to return to the RESET Vector. The PIC12F510 differentiates between various RESETS. Upon any RESET the SFR registers in Data Memory will change to a RESET value as listed in the datasheet while GPR register values will be unknown.

Master Clear Reset (MCLR) Executed by driving the GP3/MCLR/VPP pin LOW Enabled/Disabled using the configuration bits VDD VDD CPU EXECUTING CODE RESET The Master Clear Reset enables the user to manually RESET the device using a pushbutton or other signal connected to the GP3/MCLR/VPP pin that will drive that pin voltage LOW. If the Master Clear pin is not to be used it is recommended that this pin be tied to Vdd avoiding inadvertent RESETS. R V = VSS V = VDD R GP3/MCLR/VPP VSS

CPU Watchdog Timer (WDT) WDT has its own free running oscillator separate from the Main oscillator WDT will run even in SLEEP RESETS PIC should the software crash or hang WDT 1 1 1 1 1 1 STATUS Register 1 TO A supervisory feature has been added to the Baseline Microcontroller called the Watchdog Timer. This timer provides a means to detect software crashes by rolling over after a period of time (i.e. going from 2550). If the WDT overflows, the microcontroller will RESET. When properly used this feature will ensure that any software hanging results in a RESET and hopefully code execution will operate normally there after. CPU EXECUTING CODE RESET

Clears WDT to avoid overflow Resets the TO and PD bits in STATUS CLRWDT Command Clears WDT to avoid overflow WDT will only RESET PIC on overflow Resets the TO and PD bits in STATUS Clears the Prescaler RESET TO = 0? YES CLRWDT To use the WDT the Clear Watchdog Timer Command (CLRWDT) will need to be issued at some point in the application code. Clearing the WDT avoids overflow and therefore avoids RESET. NO APPLICATION CODE

Clears WDT to avoid overflow Resets the TO and PD bits in STATUS CLRWDT Command Clears WDT to avoid overflow WDT will only RESET PIC on overflow Resets the TO and PD bits in STATUS Clears the Prescaler RESET Clearing the WDT periodically ensures RESET occurs only if software HANGS TO = 0? YES CLRWDT To use the WDT the Clear Watchdog Timer Command (CLRWDT) will need to be issued at some point in the application code. Clearing the WDT avoids overflow and therefore avoids RESET. NO APPLICATION CODE

WDT Postscaler Rate Select Bits OPTION 1 1 1 1 PSA PS<2:0> The WDT Period can be configured from ~18ms to ~2.3 seconds approximately 56Hz (T = 18ms) PS<2:0> WDT RATE 000 1:1 001 1:2 010 1:4 011 1:8 100 1:16 101 1:32 110 1:64 111 1:128 Free-Running WDT Oscillator Prescaler used by Timer0 WDT is not scaled The rate at which the WDT increments can be selectable using a prescaler. There are 8 possible settings that allow the WDT overflow period to be scaled from 18mS to 2.3S depending on the application code. WDT Time-Out (Postscaler Output)

Power-up Sequence VDD sufficient to release Power On Reset (POR) Power applied to VDD VDD sufficient to release Power On Reset (POR) VDD Internal POR POR starts Device Reset Timer (DRT) Upon Power-up, a sequence of events occurs before the microcontroller will begin code execution. Two timers are used: The Internal Power-on Reset Timer (POR) and the Device RESET Timer (DRT). The POR prevents the microcontroller from executing code until the supply voltage is sufficient for the PIC to run as designed. Once the POR timer is done, the Device Reset Timer will now take over keeping the PIC in RESET to ensure that the oscillator has stabilized. Following these two timer periods, the CPU can now begin normal operation and code execution begins. MCLR DRT Period DRT

SLEEP

Executing SLEEP will: SLEEP Low-power mode to reduce power consumption Clear the WDT SET WDT Time-out bit (STATUS<TO>) CLEAR Power-down bit (STATUS<PD>) Turn off Oscillator Driver I/O Ports maintain pre-SLEEP conditions Low-power mode to reduce power consumption Executed using the SLEEP instruction SLEEP MODE NORMAL MODE + Another special feature is the ability to place the PIC microcontroller into a Low-Power SLEEP mode. During periods when the microcontroller is not required, issuing the SLEEP command will decrease power consumption and preserve battery life. BATTERY LIFE POWER CONSUMPTION

Wake-up from SLEEP Reset PIC baseline MCUs will wake from SLEEP following: MCLR reset WDT Time-out (if WDT is enabled) Change on GP0, GP1 or GP3 if wake-up on change is enabled Change in the Comparator Output (C1OUT) if wake-up on change is enabled The Baseline Microcontroller RESETs upon Wake-up Code execution begins at the RESET Vector

Using STATUS to Determine RESET GPWUF CWUF PA0 TO PD Z DC C Contains: Arithmetic status of the ALU The RESET status Program Memory Page Select Wake-up from SLEEP Flags The STATUS register contains bits that can be used to determine what condition cause the CPU to RESET. Included are General Purpose I/O and Comparator wake-up flags that indicate the RESET occurred as a result of a wake-up from SLEEP. Time-out bit indicates that RESET occurred due to a WDT overflow and the Power Down bit will SET in the event that RESET was due to a Power-up.

Using STATUS to Determine RESET GPWUF CWUF PA0 TO PD Z DC C Contains: Arithmetic status of the ALU The RESET status Program Memory Page Select Wake-up from SLEEP Flags TO – Time-out bit 0 = Reset due to WDT Time-Out PD – Power-down bit 1 = Reset due to Power up (CLRWDT will set these bits) The STATUS register contains bits that can be used to determine what condition cause the CPU to RESET. Included are General Purpose I/O and Comparator wake-up flags that indicate the RESET occurred as a result of a wake-up from SLEEP. Time-out bit indicates that RESET occurred due to a WDT overflow and the Power Down bit will SET in the event that RESET was due to a Power-up.

Using STATUS to Determine RESET GPWUF CWUF PA0 TO PD Z DC C GPWUF – General Purpose I/O Wake-up Flag 1 = Wake-up from SLEEP triggered from I/O pin change CWUF - Comparator Wake-up Flag triggered from Comparator output Contains: Arithmetic status of the ALU The RESET status Program Memory Page Select Wake-up from SLEEP Flags TO – Time-out bit 0 = Reset due to WDT Time-Out PD – Power-down bit 1 = Reset due to Power up (CLRWDT will set these bits) The STATUS register contains bits that can be used to determine what condition cause the CPU to RESET. Included are General Purpose I/O and Comparator wake-up flags that indicate the RESET occurred as a result of a wake-up from SLEEP. Time-out bit indicates that RESET occurred due to a WDT overflow and the Power Down bit will SET in the event that RESET was due to a Power-up.

Using STATUS to Determine RESET Check PD and TO bits prior to initializing any registers Initialize peripherals prior to checking GPWUF and CWUF bits MCLR reset determined if no other RESET has occurred PD = 1? Do POR RSR TO = 0? Do WDT RSR INITIALIZE PERIPHERALS GPWUF = 1? Do GPWUF RSR Using these four bits from STATUS the exact cause of the RESET can be determined through the process of elimination. Individual subroutines can further be created to address each of the RESET conditions. Always check the STATUS<PD> and STATUS<TO> flags before initializing the peripherals as they could be cleared as a result of the initialization. Furthermore, check the wake-up on change flags after the peripherals have been initialized otherwise they may not be visible. Note that if after checking all of the STATUS bits none indicate the cause of RESET it can be deduced that RESET occurred as a result of MCLR. CWUF = 1? Do CWUF RSR Do MCLR sub_routine

In-Circuit Serial Programming (ICSP)

In-Circuit Serial Programming (ICSP) PIC can be programmed in-circuit In-field firmware updates VPP VSS VDD VDD GP1/ICSPDAT GND DATA GP1/ICSPCLK CLK GP3/MCLR/VPP EXTERNAL SIGNAL CONNECTORS

__CONFIG Directive

__CONFIG _MCLRE_OFF & _CP_OFF & _WDT_OFF & _INTRC_OSC & _IOSCFS_OFF Configuration Bits Can be configured directly in MPLAB OR Added to Firmware Source File __CONFIG Directive Sets processor configuration bits Ensures desired configuration every time firmware is downloaded __CONFIG expr example: __CONFIG _MCLRE_OFF & _CP_OFF & _WDT_OFF & _INTRC_OSC & _IOSCFS_OFF ;Turns off MCLR, Code Protection and Watchdog Timer ;Configures the device for the Internal RC Oscillator at 4MHz Sets the processor's configuration bits. Before this directive is used, the processor must be declared through the command line. A complete reference for each pneumonic above is provided at the end of the Lab Manual used in today’s class.

Configuration Directive Definitions Configuration Directives are define in the “inc” file for each device found in C:\Program Files\Microchip\MPASM Suite\ The file P12F509.inc contains: ;===================================== ; Configuration Bits _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF'

Input/Output (I/O) Port

I/O Port Overview VDD VSS PIC12F510 has one General Purpose Input/Output (GPIO) register Some baseline PICs have multiple PORT registers ( PORTA, PORTB…) 5 I/O pins configurable as Input or Output using the Tri-State GPIO register TRISGPIO GP3 is input only Three of the GPIO pins GP<2:0> are configurable as analog or digital Default to analog inputs on any RESET VDD VSS TRISGPIO The first peripheral we will look at is the Input/Output PORT. The PIC12F510 has one I/O Port called the General Purpose Input Output Port (GPIO). Other members of the Baseline Family may have multiple I/O Ports. This peripheral can be used to either send or receive bit values between the PIC microcontroller and any off-chip device or circuit. GP0/AN0/C1IN+ GP5/OSC1/CLKIN GPIO GP4/OSC2 GP1/AN1/C1IN- GP3/MCLR/VPP GP2/AN2/T0CKI/C1OUT

I/O Port Schematic

GPIO and TRISGPIO Registers Two main registers General Purpose Input Output (GPIO) Tri-State GPIO (TRISGPIO) GPIO GP5 GP4 GP3 GP2 GP1 GP0 Data The GPIO register is shown in the above slide along with its corresponding data direction register TRISGPIO. GPIO contains the data to send or that has been received. Setting a bit in the TRISGPIO register will disable the output driver and make the corresponding GPIO pin and input. Clearing a bit in TRISGPIO will enable the output driver and put the contents of the latch on the selected pin. Not all pins on the PIC12F510 device are bi-directional. The GP3 pin is input only and the corresponding TRISGPIO<3> bit will always be a ‘1’. TRISGPIO TRISGP5 TRISGP4 1 TRISGP2 TRISGP1 TRISGP0 1 = corresponding GPIO pin is input 0 = corresponding GPIO pin is output

GPIO and TRISGPIO Registers Two main registers General Purpose Input Output (GPIO) Tri-State GPIO (TRISGPIO) GPIO GP5 GP4 GP3 GP2 GP1 GP0 Data Direction (write only) The GPIO register is shown in the above slide along with its corresponding data direction register TRISGPIO. GPIO contains the data to send or that has been received. Setting a bit in the TRISGPIO register will disable the output driver and make the corresponding GPIO pin and input. Clearing a bit in TRISGPIO will enable the output driver and put the contents of the latch on the selected pin. Not all pins on the PIC12F510 device are bi-directional. The GP3 pin is input only and the corresponding TRISGPIO<3> bit will always be a ‘1’. TRISGPIO TRISGP5 TRISGP4 1 TRISGP2 TRISGP1 TRISGP0 1 = corresponding GPIO pin is input 0 = corresponding GPIO pin is output

GPIO and TRISGPIO Registers Two main registers General Purpose Input Output (GPIO) Tri-State GPIO (TRISGPIO) GPIO GP5 GP4 GP3 GP2 GP1 GP0 Always Input The GPIO register is shown in the above slide along with its corresponding data direction register TRISGPIO. GPIO contains the data to send or that has been received. Setting a bit in the TRISGPIO register will disable the output driver and make the corresponding GPIO pin and input. Clearing a bit in TRISGPIO will enable the output driver and put the contents of the latch on the selected pin. Not all pins on the PIC12F510 device are bi-directional. The GP3 pin is input only and the corresponding TRISGPIO<3> bit will always be a ‘1’. TRISGPIO TRISGP5 TRISGP4 1 TRISGP2 TRISGP1 TRISGP0 1 = corresponding GPIO pin is input 0 = corresponding GPIO pin is output

General Purpose Input/Output (GPIO) Register 8-bit I/O register Only lower 6 bits are used GP<5:0> bits 7 and 6 (GP<7:6>) are unimplemented and read as 0’s Written or Read under software control I/O pins are Read independent of direction (input or output) GP5 GP4 GP3 GP2 GP1 GP0 7 0 GPIO GP5 GP0 GP4 GP1 GP3 input only GP2

Tri-State GPIO Direction Control Register (TRISGPIO) TRISGPIO (Not Addressable) 1 1 1 Pins Affected GP5 GP4 GP3 GP2 GP1 GP0 Working Register 1 1 movlw b’00111111’ TRIS GPIO movlw b’00000000’ movlw b’10101010’ INPUT INPUT GP0 Since the TRISGPIO register is not addressable, it is necessary to load this register using the TRIS assembly instruction. INPUT GP4 INPUT INPUT INPUT

Tri-State GPIO Direction Control Register (TRISGPIO) TRISGPIO (Not Addressable) 1 1 1 Pins Affected GP5 GP4 GP3 GP2 GP1 GP0 Working Register 1 OUTPUT movlw b’00111111’ TRIS GPIO movlw b’00000000’ movlw b’10101010’ OUTPUT GP5 GP0 Since the TRISGPIO register is not addressable, it is necessary to load this register using the TRIS assembly instruction. OUTPUT OUTPUT GP4 GP1 OUTPUT INPUT GP2

Tri-State GPIO Direction Control Register (TRISGPIO) TRISGPIO (Not Addressable) 1 1 1 Pins Affected GP5 GP4 GP3 GP2 GP1 GP0 Working Register 1 1 movlw b’00111111’ TRIS GPIO movlw b’00000000’ movlw b’10101010’ INPUT OUTPUT GP5 GP0 Since the TRISGPIO register is not addressable, it is necessary to load this register using the TRIS assembly instruction. OUTPUT INPUT GP4 GP1 INPUT GP3 OUTPUT GP2

Configuring I/O for Digital GP0, GP1 and GP2 are configurable for analog or digital Analog for multiplexed alternate functions comparator and analog-to-digital converter (ADC) To use GP<2:0> as digital I/O the analog alternate functions must be disabled Comparator is turned off by clearing CM1CON0<C1ON> Analog functionality is disabled by clear ADCON0 bits ANS<1:0> in the ADC module Since there are only 8 pins on the PIC12F510 and there are 4 peripherals available, some of the pins are multiplexed with alternate functions. Notably, the GP<2:0> pins are multiplexed with the comparator and analog-to-digital converter peripherals which are analog modules. Upon any RESET, these pins will automatically be configured as analog inputs. To use these pins for digital applications, these analog peripherals will need to be disabled.

Configuring I/O Pins as all Digital Clear CM1CON0<C1ON> bit (disables comparator) Clear both ANS<1:0> bits (All pins digital) CM1CON0 C1ON ADCON0 GP0/AN0/C1IN+ ANS<1:0> GP1/AN1/C1IN- GP2/AN2/T0CKI/C1OUT

1 Weak Pull-ups Configure using OPTION OPTION GP2, GP1 and GP0 pins GPPU Configure using OPTION GP2, GP1 and GP0 pins GP<2:0> must be configured as input General Purpose Pull-Up bit Pins are not independently configured VDD GP0/AN0/C1IN+ VDD GP1/AN1/C1IN- The GP<2:0> pins can be configured with weak pull-ups. This eliminates pin voltage uncertainty by ensuring that the pins will always be Vdd unless purposefully driven low. Note that either all three pins have weak pull-ups or all three do not. Also, these pins must be configured as input. VDD GP2/AN2/T0CKI/C1OUT

Wake-Up on Change RESETS/WAKES PIC from SLEEP mode OPTION RESETS/WAKES PIC from SLEEP mode GPIO must be read prior to SLEEP instruction latches current value on pins Clear GPWU in OPTION Clear GPWU in OPTION GPWU (General Purpose Wake-up) Read current GP<2:0> values Read current GP<2:0> values STATUS Issue SLEEP instruction Issue SLEEP instruction GPWUF (General Purpose Wake-up Flag) If the GPWU bit in the OPTION register is cleared and the device is placed in SLEEP mode (i.e. SLEEP command is issued in code), any change (HIGH/LOW) on GP0, GP1 and GP2 will wake and RESET the PIC. It is important to remember that similar to the comparator module, the value in GPIO will need to be read prior to issuing a SLEEP command. This will latch the current GPIO values for reference. The GP0, GP1 and GP2 pins are NOT individually configurable. Either all are set for wake-up on change or none. Note: Following RESET all registers will automatically go to their RESET default values. 1 GP5 GP4 GP3 GP2 GP1 GP0 7 0 GPIO 1

Wake-Up on Change RESETS/WAKES PIC from SLEEP mode OPTION RESETS/WAKES PIC from SLEEP mode GPIO must be read prior to SLEEP instruction latches current value on pins Clear GPWU in OPTION Clear GPWU in OPTION GPWU (General Purpose Wake-up) Read current GP<2:0> values Read current GP<2:0> values STATUS Issue SLEEP instruction Issue SLEEP instruction GPWUF (General Purpose Wake-up Flag) If the GPWU bit in the OPTION register is cleared and the device is placed in SLEEP mode (i.e. SLEEP command is issued in code), any change (HIGH/LOW) on GP0, GP1 and GP2 will wake and RESET the PIC. It is important to remember that similar to the comparator module, the value in GPIO will need to be read prior to issuing a SLEEP command. This will latch the current GPIO values for reference. The GP0, GP1 and GP2 pins are NOT individually configurable. Either all are set for wake-up on change or none. Note: Following RESET all registers will automatically go to their RESET default values. 1 GP5 GP4 GP3 GP2 GP1 GP0 7 0 GPIO 1 1 1 1 values latched for reference

Wake-Up on Change RESETS/WAKES PIC from SLEEP mode OPTION RESETS/WAKES PIC from SLEEP mode GPIO must be read prior to SLEEP instruction latches current value on pins Clear GPWU in OPTION Clear GPWU in OPTION GPWU (General Purpose Wake-up) Read current GP<2:0> values Read current GP<2:0> values STATUS Issue SLEEP instruction Issue SLEEP instruction GPWUF (General Purpose Wake-up Flag) Low-Power Mode If the GPWU bit in the OPTION register is cleared and the device is placed in SLEEP mode (i.e. SLEEP command is issued in code), any change (HIGH/LOW) on GP0, GP1 and GP2 will wake and RESET the PIC. It is important to remember that similar to the comparator module, the value in GPIO will need to be read prior to issuing a SLEEP command. This will latch the current GPIO values for reference. The GP0, GP1 and GP2 pins are NOT individually configurable. Either all are set for wake-up on change or none. Note: Following RESET all registers will automatically go to their RESET default values. 1 GP5 GP4 GP3 GP2 GP1 GP0 7 0 GPIO 1 1 1 1

1 Wake-Up on Change RESETS/WAKES PIC from SLEEP mode OPTION RESETS/WAKES PIC from SLEEP mode GPIO must be read prior to SLEEP instruction latches current value on pins Clear GPWU in OPTION Clear GPWU in OPTION GPWU (General Purpose Wake-up) Read current GP<2:0> values Read current GP<2:0> values STATUS Issue SLEEP instruction Issue SLEEP instruction 1 GPWUF (General Purpose Wake-up Flag) If the GPWU bit in the OPTION register is cleared and the device is placed in SLEEP mode (i.e. SLEEP command is issued in code), any change (HIGH/LOW) on GP0, GP1 and GP2 will wake and RESET the PIC. It is important to remember that similar to the comparator module, the value in GPIO will need to be read prior to issuing a SLEEP command. This will latch the current GPIO values for reference. The GP0, GP1 and GP2 pins are NOT individually configurable. Either all are set for wake-up on change or none. Note: Following RESET all registers will automatically go to their RESET default values. RESET 1 GP5 GP4 GP3 GP2 GP1 GP0 7 0 GPIO 1 1 1 1 GP1 state change

Read-Modify-Write for Bit Instructions GPIO 1 1 VGP4 pin D Q GP4 LATCH CPU HIGH (1) READ GP4 pin LOW (1) TRISGP4 CONFIGURED AS OUTPUT GPIO pin values 1 1 1 In the above diagram, the switches are used to represent a simplification of logic circuitry containing latches, AND/OR gates, CMOS transistors, tri-state buffers and so on. Basically, these can be equated to a switch. This diagram is a very simplified view of an I/O port. This does not take into account peripheral functions that may be multiplexed onto the I/O pin. Reading the GPIO register reads the status of the pins whereas writing to it will write to the port latch. All single bit manipulation instructions are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. This slide demonstrates the read-modify-write characteristic of the PORT pins on the PIC Microcontroller. Essentially, any bit instruction will cause the CPU to first read the PORT pin regardless of whether it is configured as input or output. The output of the PORT is latched meaning that it will remember the last output value sent to it by the CPU until the CPU changes it. This could cause unknown values in the GPIO register if the CPU is processing information faster than the pin can change its logic level (i.e. if interface circuitry to the pin produces a capacitance). In the above slide the pin voltage is shown in the graph immediately to its right. Performing a bit instruction such as clearing the GP4 bit causes the CPU to first read the current pin voltage, modify it by clearing it, and then finally write this value to the GP4 latch. If a subsequent bit command is issued before the GP4 pin voltage has time to drop to a logic level LOW, the GP4 pin will be read as a logic HIGH. Keeping this in mind let’s consider a solution. Note that even if the GP4 pin corresponding TRISGP4 was configured as an input, the GP4 pin value would still be readable. Since pin voltages are read, this could generate an unexpected bit value in the PORT register. This could occur as a result of a high oscillator frequency or capacitance on pin which slows voltage response. Clear GPIO bit 4 DATA BUS Read GP4

Read-Modify-Write for Bit Instructions GPIO 1 1 VGP4 pin D Q GP4 LATCH CPU HIGH (1) MODIFY GP4 pin LOW (1) TRISGP4 CONFIGURED AS OUTPUT GPIO pin values 1 1 In the above diagram, the switches are used to represent a simplification of logic circuitry containing latches, AND/OR gates, CMOS transistors, tri-state buffers and so on. Basically, these can be equated to a switch. This diagram is a very simplified view of an I/O port. This does not take into account peripheral functions that may be multiplexed onto the I/O pin. Reading the GPIO register reads the status of the pins whereas writing to it will write to the port latch. All single bit manipulation instructions are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. This slide demonstrates the read-modify-write characteristic of the PORT pins on the PIC Microcontroller. Essentially, any bit instruction will cause the CPU to first read the PORT pin regardless of whether it is configured as input or output. The output of the PORT is latched meaning that it will remember the last output value sent to it by the CPU until the CPU changes it. This could cause unknown values in the GPIO register if the CPU is processing information faster than the pin can change its logic level (i.e. if interface circuitry to the pin produces a capacitance). In the above slide the pin voltage is shown in the graph immediately to its right. Performing a bit instruction such as clearing the GP4 bit causes the CPU to first read the current pin voltage, modify it by clearing it, and then finally write this value to the GP4 latch. If a subsequent bit command is issued before the GP4 pin voltage has time to drop to a logic level LOW, the GP4 pin will be read as a logic HIGH. Keeping this in mind let’s consider a solution. Note that even if the GP4 pin corresponding TRISGP4 was configured as an input, the GP4 pin value would still be readable. Since pin voltages are read, this could generate an unexpected bit value in the PORT register. This could occur as a result of a high oscillator frequency or capacitance on pin which slows voltage response. Clear GPIO bit 4 DATA BUS Read GP4

Read-Modify-Write for Bit Instructions Pin voltage begins to change slowly GPIO 1 VGP4 pin D Q GP4 LATCH CPU HIGH (1) WRITE GP4 pin LOW (1) TRISGP4 CONFIGURED AS OUTPUT GPIO pin values 1 1 In the above diagram, the switches are used to represent a simplification of logic circuitry containing latches, AND/OR gates, CMOS transistors, tri-state buffers and so on. Basically, these can be equated to a switch. This diagram is a very simplified view of an I/O port. This does not take into account peripheral functions that may be multiplexed onto the I/O pin. Reading the GPIO register reads the status of the pins whereas writing to it will write to the port latch. All single bit manipulation instructions are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. This slide demonstrates the read-modify-write characteristic of the PORT pins on the PIC Microcontroller. Essentially, any bit instruction will cause the CPU to first read the PORT pin regardless of whether it is configured as input or output. The output of the PORT is latched meaning that it will remember the last output value sent to it by the CPU until the CPU changes it. This could cause unknown values in the GPIO register if the CPU is processing information faster than the pin can change its logic level (i.e. if interface circuitry to the pin produces a capacitance). In the above slide the pin voltage is shown in the graph immediately to its right. Performing a bit instruction such as clearing the GP4 bit causes the CPU to first read the current pin voltage, modify it by clearing it, and then finally write this value to the GP4 latch. If a subsequent bit command is issued before the GP4 pin voltage has time to drop to a logic level LOW, the GP4 pin will be read as a logic HIGH. Keeping this in mind let’s consider a solution. Note that even if the GP4 pin corresponding TRISGP4 was configured as an input, the GP4 pin value would still be readable. Since pin voltages are read, this could generate an unexpected bit value in the PORT register. This could occur as a result of a high oscillator frequency or capacitance on pin which slows voltage response. Clear GPIO bit 4 DATA BUS Read GP4

Read-Modify-Write for Bit Instructions GPIO 1 VGP4 pin D Q GP4 LATCH CPU HIGH (1) READ GP4 pin LOW (1) TRISGP4 CONFIGURED AS OUTPUT GPIO pin values 1 1 1 In the above diagram, the switches are used to represent a simplification of logic circuitry containing latches, AND/OR gates, CMOS transistors, tri-state buffers and so on. Basically, these can be equated to a switch. This diagram is a very simplified view of an I/O port. This does not take into account peripheral functions that may be multiplexed onto the I/O pin. Reading the GPIO register reads the status of the pins whereas writing to it will write to the port latch. All single bit manipulation instructions are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. This slide demonstrates the read-modify-write characteristic of the PORT pins on the PIC Microcontroller. Essentially, any bit instruction will cause the CPU to first read the PORT pin regardless of whether it is configured as input or output. The output of the PORT is latched meaning that it will remember the last output value sent to it by the CPU until the CPU changes it. This could cause unknown values in the GPIO register if the CPU is processing information faster than the pin can change its logic level (i.e. if interface circuitry to the pin produces a capacitance). In the above slide the pin voltage is shown in the graph immediately to its right. Performing a bit instruction such as clearing the GP4 bit causes the CPU to first read the current pin voltage, modify it by clearing it, and then finally write this value to the GP4 latch. If a subsequent bit command is issued before the GP4 pin voltage has time to drop to a logic level LOW, the GP4 pin will be read as a logic HIGH. Keeping this in mind let’s consider a solution. Note that even if the GP4 pin corresponding TRISGP4 was configured as an input, the GP4 pin value would still be readable. Since pin voltages are read, this could generate an unexpected bit value in the PORT register. This could occur as a result of a high oscillator frequency or capacitance on pin which slows voltage response. Bit 4 read as 1 due to slow transition Set GPIO bit 0 DATA BUS Read GP4

Read-Modify-Write for Bit Instructions GPIO 1 1 VGP4 pin D Q GP4 LATCH CPU HIGH (1) MODIFY GP4 pin LOW (1) TRISGP4 CONFIGURED AS OUTPUT GPIO pin values 1 1 1 Pin 4 read as high due to slow transition In the above diagram, the switches are used to represent a simplification of logic circuitry containing latches, AND/OR gates, CMOS transistors, tri-state buffers and so on. Basically, these can be equated to a switch. This diagram is a very simplified view of an I/O port. This does not take into account peripheral functions that may be multiplexed onto the I/O pin. Reading the GPIO register reads the status of the pins whereas writing to it will write to the port latch. All single bit manipulation instructions are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. This slide demonstrates the read-modify-write characteristic of the PORT pins on the PIC Microcontroller. Essentially, any bit instruction will cause the CPU to first read the PORT pin regardless of whether it is configured as input or output. The output of the PORT is latched meaning that it will remember the last output value sent to it by the CPU until the CPU changes it. This could cause unknown values in the GPIO register if the CPU is processing information faster than the pin can change its logic level (i.e. if interface circuitry to the pin produces a capacitance). In the above slide the pin voltage is shown in the graph immediately to its right. Performing a bit instruction such as clearing the GP4 bit causes the CPU to first read the current pin voltage, modify it by clearing it, and then finally write this value to the GP4 latch. If a subsequent bit command is issued before the GP4 pin voltage has time to drop to a logic level LOW, the GP4 pin will be read as a logic HIGH. Keeping this in mind let’s consider a solution. Note that even if the GP4 pin corresponding TRISGP4 was configured as an input, the GP4 pin value would still be readable. Since pin voltages are read, this could generate an unexpected bit value in the PORT register. This could occur as a result of a high oscillator frequency or capacitance on pin which slows voltage response. Set GPIO bit 0 DATA BUS Read GP4

Read-Modify-Write for Bit Instructions GPIO 1 1 VGP4 pin D Q GP4 LATCH CPU HIGH (1) WRITE 1 GP4 pin LOW (1) TRISGP4 CONFIGURED AS OUTPUT GPIO pin values 1 1 1 In the above diagram, the switches are used to represent a simplification of logic circuitry containing latches, AND/OR gates, CMOS transistors, tri-state buffers and so on. Basically, these can be equated to a switch. This diagram is a very simplified view of an I/O port. This does not take into account peripheral functions that may be multiplexed onto the I/O pin. Reading the GPIO register reads the status of the pins whereas writing to it will write to the port latch. All single bit manipulation instructions are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. This slide demonstrates the read-modify-write characteristic of the PORT pins on the PIC Microcontroller. Essentially, any bit instruction will cause the CPU to first read the PORT pin regardless of whether it is configured as input or output. The output of the PORT is latched meaning that it will remember the last output value sent to it by the CPU until the CPU changes it. This could cause unknown values in the GPIO register if the CPU is processing information faster than the pin can change its logic level (i.e. if interface circuitry to the pin produces a capacitance). In the above slide the pin voltage is shown in the graph immediately to its right. Performing a bit instruction such as clearing the GP4 bit causes the CPU to first read the current pin voltage, modify it by clearing it, and then finally write this value to the GP4 latch. If a subsequent bit command is issued before the GP4 pin voltage has time to drop to a logic level LOW, the GP4 pin will be read as a logic HIGH. Keeping this in mind let’s consider a solution. Note that even if the GP4 pin corresponding TRISGP4 was configured as an input, the GP4 pin value would still be readable. Since pin voltages are read, this could generate an unexpected bit value in the PORT register. This could occur as a result of a high oscillator frequency or capacitance on pin which slows voltage response. Set GPIO bit 0 DATA BUS Read GP4

Shadowing a PORT Register DATA MEMORY INDF Create a Shadow register in General Purpose RAM TMR0 PCL STATUS FSR SFRs OSCCAL Perform any single bit changes to the Shadow Register 1 GPIO CM1CON0 ADCON0 ADRES A solution to RMW is the use of shadow registers. Copy the value into the PORT Register user_reg GPRs 1 user defined shadow register

Timer0

Timer0 Overview Increments a register called TMR0 using a clock source Can be configured to: Increments using the internal instruction cycles (TCY) Increments using the output of the comparator CM1CON0<C1OUT> bit Increments using external source on Timer0 Clock In pin (T0CKI) Clock source is configurable using a prescaler VDD VSS TMR0 GP5/OSC1/CLKIN GP0/AN0/C1IN+ GP4/OSC2 PRESCALER GP1/AN1/C1IN- TCY or C1OUT GP3/MCLR/VPP GP2/AN2/T0CKI/C1OUT

Timer0 module can be used as follows: Timer0 Applications Timer0 module can be used as follows: A timer Time an Event Implement a Clock Event counter Count an event Start Timing Stop Timing The TMR0 register can be configured to increment based on the instruction clock (TCY). This configures the Timer0 module as a timer. Using the FOSC/4 instruction cycle as a known time base, Timer0 can then be used to time and event or implement a clock. When configured as a counter, the TMR0 will increment based on the transition of an input signal from either the T0CKI pin or the output of the comparator. The Timer0 module can then be used to effectively count signal transitions from either of these two sources. TMR0 1 1 1 1 1 1 1 1

Registers Associated with Timer0 OPTION RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 Configures Timer0 Module BIT FUNCTION T0CS Timer0 Clock Source Select bit 1 = T0CKI pin 0 = Internal clock T0SE Timer0 Source Edge bit 1 = high-to-low transition 0 = low-to-high transition PSA Prescaler Assignment bit 1 = Assigned to WDT 0 = Assigned to Timer0 PS<2:0> Prescaler Rate Select bits

Loading the OPTION Register 1 GPWU GPPU T0CS TOSE PSA PS2 PS1 PS0 Wreg 1 ;Load desired value into Wreg using inline assembly then issue ;OPTION instruction to load OPTION register movlw b’00110001 ;move desired value into W OPTION ;move value in W into OPTION The OPTION register, same as the TRISGPIO register, is not addressable directly. Therefore, the only way to configure this register is to first load the desired value into the Working register and then issue the Baseline specific OPTION instruction to move the Working Register value into the OPTION register.

Registers Associated with Timer0 TMR0 8-bit timer/counter register Holds the count or time value for the Timer0 module CM1CON0 C1T0CS Comparator TMR0 Clock Source bit When this bit is cleared to 0, comparator 1 output is used as TMR0 clock source The TMR0 register is where the current count value is held. A predetermined transition on the clock source to this register, FOSC/4 or T0CKI pin or Comparator output, will increment this register sequentially. As was mentioned previously, we can configure the Comparator output to be used as the clock source for the TMR0 register. More on this later.

TMR0 Block Diagram 8 1 1 1 1 1 1 1 1 1 1 TMR0 CM1CON0 OPTION FOSC/4 8 RC5/T0CKI Sync 1 1 1 1 1 Comparator Output (C1OUT) prescaler prescaler prescaler prescaler TMR0 T0SE C1T0CS T0CS PS<2:0> PS<2:0> PSA CM1CON0 OPTION The above block diagram steps through each of the Timer0 control bits in both CM1CON0 and OPTION to graphically show the purpose of each. 1 1 1 1 1 C1T0CS Comparator TMR0 Clock Source Bit 1 = TMR0 source is T0CKI pin or FOSC/4 0 = TMR0 is the comparator

TMR0 Block Diagram 8 1 1 1 1 1 1 1 1 1 TMR0 CM1CON0 OPTION FOSC/4 8 RC5/T0CKI Sync 1 1 1 1 1 Comparator Output (C1OUT) prescaler prescaler TMR0 T0SE T0CS PS<2:0> C1T0CS PSA CM1CON0 OPTION The above block diagram steps through each of the Timer0 control bits in both CM1CON0 and OPTION to graphically show the purpose of each. 1 1 1 1 C1T0CS Comparator TMR0 Clock Source Bit 1 = TMR0 source is T0CKI pin or FOSC/4 0 = TMR0 is the comparator

TMR0 Block Diagram 8 x 1 1 1 1 1 1 1 1 1 TMR0 CM1CON0 OPTION FOSC/4 8 RC5/T0CKI Sync 1 1 1 1 1 Comparator Output (C1OUT) prescaler prescaler TMR0 T0SE T0CS PS<2:0> C1T0CS PSA CM1CON0 OPTION The above block diagram steps through each of the Timer0 control bits in both CM1CON0 and OPTION to graphically show the purpose of each. 1 x 1 1 1 TMR0 Source Edge Select Bit 1 = Increment TMR0 on high – low transition of TOCKi 0 = Increment TMR

TMR0 Block Diagram 8 Comparator output or T0CKI pin 1 1 1 1 1 1 1 1 1 FOSC/4 8 Comparator output or T0CKI pin RC5/T0CKI Sync 1 1 1 1 1 Comparator Output (C1OUT) prescaler prescaler TMR0 T0SE T0CS PS<2:0> C1T0CS PSA CM1CON0 OPTION The above block diagram steps through each of the Timer0 control bits in both CM1CON0 and OPTION to graphically show the purpose of each. 1 1 1 1 1 T0CS TMR0 Clock Source Select bit 1 = Selects either C1OUT or T0CKI as input to TMR0 0 = Selects Fosc/4 as TMR0 clock source

TMR0 Block Diagram 8 1 1 1 1 1 1 1 1 1 TMR0 CM1CON0 OPTION T0CS FOSC/4 8 RC5/T0CKI Sync 1 1 1 1 1 Comparator Output (C1OUT) prescaler prescaler TMR0 T0SE T0CS PS<2:0> C1T0CS PSA CM1CON0 OPTION The above block diagram steps through each of the Timer0 control bits in both CM1CON0 and OPTION to graphically show the purpose of each. 1 1 1 1 T0CS TMR0 Clock Source Select bit 1 = Selects either C1OUT or T0CKI as input to TMR0 0 = Selects Fosc/4 as TMR0 clock source

TMR0 Block Diagram 8 not scaled 1 1 1 1 1 1 1 1 1 1 TMR0 CM1CON0 FOSC/4 8 not scaled RC5/T0CKI Sync 1 1 1 1 1 Comparator Output (C1OUT) prescaler prescaler TMR0 T0SE T0CS PS<2:0> C1T0CS PSA CM1CON0 OPTION The above block diagram steps through each of the Timer0 control bits in both CM1CON0 and OPTION to graphically show the purpose of each. 1 1 1 1 1 PSA TMR0 Clock Source Select bit 1 = Selects either C1OUT or T0CKI as input to TMR0 0 = Selects Fosc/4 as TMR0 clock source

TMR0 Block Diagram 8 1 1 1 1 1 Scaled 1 1 1 1 TMR0 CM1CON0 OPTION PSA FOSC/4 8 RC5/T0CKI Sync 1 1 1 1 1 Comparator Output (C1OUT) Scaled prescaler prescaler TMR0 T0SE T0CS PS<2:0> C1T0CS PSA CM1CON0 OPTION The above block diagram steps through each of the Timer0 control bits in both CM1CON0 and OPTION to graphically show the purpose of each. 1 1 1 1 PSA TMR0 Clock Source Select bit 1 = Selects either C1OUT or T0CKI as input to TMR0 0 = Selects Fosc/4 as TMR0 clock source

TMR0 Block Diagram 8 1 1 1 1 1 1 1 1 1 x x TMR0 CM1CON0 OPTION x PSA FOSC/4 8 RC5/T0CKI Sync 1 1 1 1 1 Comparator Output (C1OUT) prescaler prescaler TMR0 T0SE BIT VALUE Timer0 RATE 000 1:2 001 1:4 010 1:8 011 1:16 100 1:32 101 1:64 110 1:128 111 1:256 PS<2:0> C1T0CS T0CS PSA CM1CON0 OPTION The above block diagram steps through each of the Timer0 control bits in both CM1CON0 and OPTION to graphically show the purpose of each. 1 1 1 1 x x x PSA PS<2:0> PreScaler Rate Select Bits PSA must be 0

Synchronizes signal with internal clock TMR0 Block Diagram Synchronizes signal with internal clock FOSC/4 8 RC5/T0CKI Sync 1 1 1 1 1 Comparator Output (C1OUT) prescaler prescaler T0SE TMR0 C1T0CS T0CS PS<2:0> PSA CM1CON0 OPTION The above block diagram steps through each of the Timer0 control bits in both CM1CON0 and OPTION to graphically show the purpose of each. 1

Synchronizing Timer0 with an External Clock Internal Clock TMR0 Sync. with Internal Clock TOSC PRESCALER Ext. Clock Period must be > 4xTOSC _ T0CKI External Clock/Prescaler Output For the external clock source to meet the sampling requirement, it is necessary for T0CKI or the comparator output to have a period of at least 4TOSC when using the prescaler. The input clock signal is sampled every second TOSC. Note that the initial TMR0 value will need to be sampled and then written. While the current value of TMR0 is being written the next TMR0 value is being sampled. Internal synchronization samples every 2nd TOSC TMR0 TMR0 + 1 TMR0 + 2

Writing to TMR0 inhibits increment for two clock cycles CLEAR TMR0 Register TMR0 SOURCE CLOCK WRITE 00001111 to TMR0 Writing to the TMR0 register will cause a two cycle delay in the new value being shown in the TMR0 register. This is due to the fact the new TMR0 value must first be read and then written into TMR0 register. Any code that writes to TMR0 will need to address this with an offset in time sensitive applications. TMR0+1 TMR0+2 READ New TMR0 NEW TMR0 TMR0+1 TMR0+2 TMR0 Register 1 1 1 1 1 continue

Analog-to-Digital Converter (ADC)

Analog-to-Digital Converter (ADC) Overview Converts an analog signal to an 8-bit value Stores this value in the ADC Result register ADRES Controlled by ADC Control register ADCON0 Configurable conversion clock (TAD) Conversions compared against VDD 3 analog input channels (AN0, AN1, or AN2) VDD ADRES VDD VSS ADC AN0, AN1 or AN2 8 GP5/OSC1/CLKIN GP0/AN0/C1IN+ GP4/OSC2 GP1/AN1/C1IN- ADC Conversion Clock GP3/MCLR/VPP GP2/AN2/C1OUT

Provide a means of decoding transducer output Designing with ADCs Provide a means of decoding transducer output Pressure sensors Thermocouples etc… Variable DC Measurement More suitable for recognizing slower analog signal transitions than comparator ADRES 1 1 ADC 8 VIN time ADRES 1 1 1 1

Analog-to-Digital Converter Control Register ( ADCON0) ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON Analog Input Pin Select ANS1 ANS0 Pin configured as Analog Input None 1 GP2/AN2 GP2/AN2 and GP0/AN0 GP2/AN2, GP1/AN1 and GP0/AN0

Analog-to-Digital Converter Control Register ( ADCON0) ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON ADC Conversion Clock Select ADCS1 ADCS0 Conversion Clock Rate FOSC/32 1 FOSC/16 FOSC/8 INTOSC/8

Analog-to-Digital Converter Control Register ( ADCON0) ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON ADC Channel Select CHS1 CHS0 ADC Channel Channel 00 (GP0/AN0) 1 Channel 01 (GP1/AN1) Channel 10 (GP2/AN2) 0.6V absolute voltage reference

Analog-to-Digital Converter Control Register ( ADCON0) ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON ADC Channel Select GO/DONE 1 = Starts a conversion process. Cleared by hardware when conversion is complete 0 = Manually clearing will terminate a conversion ADON 1 = ADC Module is ON 0 = ADC Module is OFF

Analog-to-Digital Converter Control Register ( ADCON0) ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON BIT FUNCTION ANS<1:0> Analog Input Pin Select bits ADCS<1:0> ADC Conversion Clock Select bits CHS<1:0> ADC Channel Select bits GO/DONE 1 = Starts a conversion process. Cleared by hardware when conversion is complete 0 = Manually clearing will terminate a conversion ADON 1 = ADC Module is ON 0 = ADC Module is OFF

Analog-to-Digital Result Register (ADRES) 8-bit value is stored in result register (ADRES) Value represents analog signal as it compares to a reference voltage (VDD) ADRES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 To read the ADRES register it is important to understand the significance of each bit position. Each bit will represent a fractional portion of the reference voltage which in this case is Vdd. The MSB ADRES<7> represents ½ Vdd, ADRES<6> represents ½ of that and so on. When a result is obtained from ADRES, simply take each bit position that is SET (=1) and add them together to obtain your result.

Analog-to-Digital Result Register (ADRES) 8-bit value is stored in result register (ADRES) Value represents analog signal as it compares to a reference voltage (VDD) ADRES To read the ADRES register it is important to understand the significance of each bit position. Each bit will represent a fractional portion of the reference voltage which in this case is Vdd. The MSB ADRES<7> represents ½ Vdd, ADRES<6> represents ½ of that and so on. When a result is obtained from ADRES, simply take each bit position that is SET (=1) and add them together to obtain your result.

Analog-to-Digital Result Register (ADRES) 8-bit value is stored in result register (ADRES) Value represents analog signal as it compares to a reference voltage (VDD) Example: ADRES = 1000 1010 and VDD = 5V Analog input voltage is + = + + = 2.7V ADRES To read the ADRES register it is important to understand the significance of each bit position. Each bit will represent a fractional portion of the reference voltage which in this case is Vdd. The MSB ADRES<7> represents ½ Vdd, ADRES<6> represents ½ of that and so on. When a result is obtained from ADRES, simply take each bit position that is SET (=1) and add them together to obtain your result.

ADC Block Diagram ADC = 1 1 1 1 1 Conversion Clock GP0/AN0 pin ADRES The above block diagram shows the effect of each bit in the Analog-to-Digital Converter Control (ADCON0) register on the module. ADCON0 CHS <1:0> 1 1 1 1 1 0.6VREF ADC Enable Bit 1 = ADC module in operating (consuming power) 0 = ADC module is shut-off (not consuming power) ADON

ADC Block Diagram ADC All pins digital 1 GP2/AN2 is analog ANS1 ANS0 Result All pins digital 1 GP2/AN2 is analog GP2/AN2 and GP0/AN0 are analog GP2/AN2, GP1/AN1 and GP0/AN0 are all analog = Conversion Clock GP0/AN0 pin ADC GP1/AN1 pin GP2/AN2 pin ADRES The above block diagram shows the effect of each bit in the Analog-to-Digital Converter Control (ADCON0) register on the module. ADCON0 CHS <1:0> x 1 1 x 1 1 0.6VREF ANS<1:0> ADC Analog Input Select Bits

0.6V absolute voltage reference ADC Block Diagram = CHS1 CHS0 CHANNEL SELECTED Channel 00 (GP0/AN0) 1 Channel 01 (GP1/AN1) Channel 02 (GP2/AN2) 0.6V absolute voltage reference Conversion Clock GP0/AN0 pin ADC GP1/AN1 pin GP2/AN2 pin ADRES The above block diagram shows the effect of each bit in the Analog-to-Digital Converter Control (ADCON0) register on the module. ADCON0 CHS <1:0> 1 1 1 1 X X 0.6VREF CHS<1:0> ADC Channel Select Bits

ADC Block Diagram ADC 1 INTosc/8 = ADCS1 ADCS0 Conversion Clock Fosc/32 1 Fosc/16 Fosc/8 INTosc/8 GP0/AN0 pin ADC GP1/AN1 pin GP2/AN2 pin ADRES The above block diagram shows the effect of each bit in the Analog-to-Digital Converter Control (ADCON0) register on the module. ADCON0 CHS <1:0> 1 1 1 1 X X 0.6VREF CHS<1:0> ADC Channel Select Bits

Input Signal Acquisition Time Conversion Time time VC VIN ADRES 8 time ADC Acquisition Time allows Hold Capacitor time to fully charge to VIN refer to the data sheet for oscillator specific timing requirements In order to get an accurate ADC conversion result, we must respect some time periods. First, the acquisition time allows a charging capacitor within the ADC module to fully charge. The ADC conversion will actually be performed on the charged capacitor value. + VC - CHOLD 120pF VSS

Conversion Time ADC Result ADC time VC time time VIN ADRES Acquisition Time Acquisition Time Conversion Time time VC VIN ADRES ADC Result 8 time 13 ADC Conversion Clock cycles (TAD) ADC Once the acquisition time is completed, the charged capacitor voltage is converted into an 8-bit value. Note that a total of 13 conversion clock cycles will be needed to accurately convert a value. Once again, refer to the datasheet for your specific device and oscillator. On the thirteenth clock cycle the 8-bit conversion value is loaded into ADRES. time + VC - CHOLD 5pF VSS

Analog-to-Digital Conversion ADCON0 1 1 1 ADC Flow GO/DONE ADON Configure ADCON0 ensuring that ADC is turned on Configure ADCON0 ensuring that ADC is turned on Conversion Time Start ADC conversion by setting the GO/DONE bit Start ADC conversion by setting the GO/DONE bit Putting it all together, an ADC conversion will begin by setting the GO/DONE bit HIGH (=1). A loop is set-up that continuously checks the GO/DONE bit and once it CLEARS (=0) this indicates the conversion is completed. At this point ADRES can be read to retrieve the 8-bit result. If a conversion is in progress and the GO/DONE bit is manually cleared, only a partial ADC conversion result will be stored in ADRES GO/DONE = 0? GO/DONE = 0? NO YES ADRES continue continue

Analog-to-Digital Conversion ADCON0 1 1 1 ADC Flow GO/DONE ADON Configure ADCON0 ensuring that ADC is turned on Configure ADCON0 ensuring that ADC is turned on Conversion Time Start ADC conversion by setting the GO/DONE bit Start ADC conversion by setting the GO/DONE bit Putting it all together, an ADC conversion will begin by setting the GO/DONE bit HIGH (=1). A loop is set-up that continuously checks the GO/DONE bit and once it CLEARS (=0) this indicates the conversion is completed. At this point ADRES can be read to retrieve the 8-bit result. If a conversion is in progress and the GO/DONE bit is manually cleared, only a partial ADC conversion result will be stored in ADRES GO/DONE = 0? GO/DONE = 0? NO YES ADRES continue continue

Analog-to-Digital Conversion ADCON0 1 1 1 ADC Flow GO/DONE ADON Configure ADCON0 ensuring that ADC is turned on Configure ADCON0 ensuring that ADC is turned on Acquisition Time Conversion Time Setting the GO/DONE bit starts a conversion Manually clearing the GO/DONE bit aborts a conversion Start ADC conversion by setting the GO/DONE bit Start ADC conversion by setting the GO/DONE bit 13 ADC Clock cycles (TAD) Putting it all together, an ADC conversion will begin by setting the GO/DONE bit HIGH (=1). A loop is set-up that continuously checks the GO/DONE bit and once it CLEARS (=0) this indicates the conversion is completed. At this point ADRES can be read to retrieve the 8-bit result. If a conversion is in progress and the GO/DONE bit is manually cleared, only a partial ADC conversion result will be stored in ADRES GO/DONE = 0? GO/DONE = 0? NO YES ADRES continue continue PARTIAL RESULT

Analog-to-Digital Conversion ADCON0 1 1 1 ADC Flow GO/DONE ADON Configure ADCON0 ensuring that ADC is turned on Configure ADCON0 ensuring that ADC is turned on Acquisition Time Conversion Time Start ADC conversion by setting the GO/DONE bit Start ADC conversion by setting the GO/DONE bit Putting it all together, an ADC conversion will begin by setting the GO/DONE bit HIGH (=1). A loop is set-up that continuously checks the GO/DONE bit and once it CLEARS (=0) this indicates the conversion is completed. At this point ADRES can be read to retrieve the 8-bit result. If a conversion is in progress and the GO/DONE bit is manually cleared, only a partial ADC conversion result will be stored in ADRES GO/DONE = 0? GO/DONE = 0? NO YES ADRES continue continue

Analog-to-Digital Conversion ADCON0 1 1 1 ADC Flow GO/DONE ADON Configure ADCON0 ensuring that ADC is turned on Configure ADCON0 ensuring that ADC is turned on Acquisition Time Conversion Time Start ADC conversion by setting the GO/DONE bit Start ADC conversion by setting the GO/DONE bit 13 ADC Clock cycles (TAD) Putting it all together, an ADC conversion will begin by setting the GO/DONE bit HIGH (=1). A loop is set-up that continuously checks the GO/DONE bit and once it CLEARS (=0) this indicates the conversion is completed. At this point ADRES can be read to retrieve the 8-bit result. If a conversion is in progress and the GO/DONE bit is manually cleared, only a partial ADC conversion result will be stored in ADRES GO/DONE = 0? GO/DONE = 0? NO YES ADRES continue continue Full RESULT CONVERSION RESULT

ADC is unable to do any conversion in SLEEP ADC in SLEEP Mode ADC is unable to do any conversion in SLEEP If a conversion is in process when SLEEP command is issued, ADRES will contain partial conversion data ADCS and CHS bits are reset to default conditions The ADC does not have its own dedicated oscillator and relies entirely on the device oscillator FOSC. Therefore, the ADC cannot operate in SLEEP. All SFR registers including ADCON0 have a default value that is loaded on any RESET. Refer to the datasheet for the particular device you are using for these values.

Comparator

Comparator Overview + _ Compares two reference input voltages If the two voltages differ, comparator output will change Configured using the comparator control register CM1CON0 Comparator changes are indicated on the CM1CON0<C1OUT> bit VDD VSS + _ GP5/OSC1/CLKIN GP0/AN0/C1IN+ GP4/OSC2 GP1/AN1/C1IN- C1OUT GP3/MCLR/VPP GP2/AN2/T0CKI/C1OUT

Comparator Overview + _ Positive Reference Voltage (C1IN+) Negative Reference (C1IN-) Positive reference (C1IN+) + _ Output (C1OUT) Negative Reference (C1IN-) Output (C1OUT) A comparator compares to input reference values and produces an output (either 1 or 0) on the output based on that comparison. The comparator on the PIC12F510 will compare the positive reference input to the negative reference.

Designing with Comparators Low/High Voltage Detection Window Comparison Pulse Counter Comparator output can be connected to Timer0 module Configurable as an OPAMP in cost sensitive applications external components required *Refer to “PICmicro Comparator Tips ‘n Tricks” at www.microchip.com

Comparator Control Register (CM1CON0) C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU BIT FUNCTION C1OUT Comparator Output Bit *READ ONLY C1OUTEN 1 = C1OUT is read internally only 0 = C1OUT value is available on C1OUT pin C1POL 0 = comparator output is inverted C1T0CS 0 = Comparator output used as TMR0 clock source C1ON 1 = Comparator is ON C1NREF 1 = Comparator Negative reference is the C1IN- pin 0 = Negative reference is the 0.6V internal reference C1PREF 1 = Comparator Positive reference is the C1IN+ pin 0 = Comparator Positive reference is the C1IN- pin C1WUF 1 = Comparator Wake-up on change is disabled

Comparator Block Diagram C1IN+ pin C1PREF Data Bus + _ C1IN- pin C1OUT pin C1POL C1OUTEN 0.6VREF C1NREF The above block diagram demonstrates the effect of manipulating bits within CM1CON0 on the comparator module. CM1CON0 1 C1ON Comparator Enable Bit 1 = Comparator module is ON 0 = Comparator module is OFF

Comparator Block Diagram C1IN+ pin C1PREF Data Bus + _ C1IN- pin C1OUT pin C1POL C1OUTEN C1NREF The above block diagram demonstrates the effect of manipulating bits within CM1CON0 on the comparator module. 0.6VREF CM1CON0 C1PREF 1 C1PREF Comparator Positive Reference Select Bit 1 = C1IN+ pin 0 = C1IN- pin

Comparator Block Diagram C1IN+ pin C1PREF Data Bus + _ C1IN- pin C1OUT pin C1OUTEN C1POL C1NREF The above block diagram demonstrates the effect of manipulating bits within CM1CON0 on the comparator module. 0.6VREF CM1CON0 C1PREF C1PREF Comparator Positive Reference Select Bit 1 = C1IN+ pin 0 = C1IN- pin

Comparator Block Diagram C1IN+ pin C1PREF Data Bus + _ C1IN- pin C1OUT pin C1OUTEN C1POL C1NREF The above block diagram demonstrates the effect of manipulating bits within CM1CON0 on the comparator module. 0.6VREF CM1CON0 C1PREF 1 C1NREF Comparator Negative Reference Select Bit 1 = C1IN- pin 0 = 0.6 internal reference voltage

Comparator Block Diagram C1IN+ pin C1PREF Data Bus + _ C1IN- pin C1OUT pin C1OUTEN C1POL C1NREF The above block diagram demonstrates the effect of manipulating bits within CM1CON0 on the comparator module. 0.6VREF CM1CON0 C1PREF C1NREF Comparator Negative Reference Select Bit 1 = C1IN- pin 0 = 0.6 internal reference voltage

Comparator Block Diagram When positive reference voltage is greater than negative reference voltage C1OUT pin voltage = 1 C1IN+ pin C1PREF Data Bus + _ C1IN- pin C1OUT pin C1OUTEN C1POL C1NREF The above block diagram demonstrates the effect of manipulating bits within CM1CON0 on the comparator module. 0.6VREF CM1CON0 C1PREF 1 C1POL Comparator Output Polarity Bit 1 = Output of Comparator is not inverted 0 = Output of Comparator is inverted

Comparator Block Diagram When positive reference voltage is greater than negative reference voltage C1OUT pin voltage = 0 C1IN+ pin C1PREF Data Bus + _ C1IN- pin C1OUT pin C1OUTEN C1POL C1NREF The above block diagram demonstrates the effect of manipulating bits within CM1CON0 on the comparator module. 0.6VREF CM1CON0 C1PREF C1POL Comparator Output Polarity Bit 1 = Output of Comparator is not inverted 0 = Output of Comparator is inverted

Comparator Block Diagram Comparator output (C1OUT) is available only internally C1IN+ pin C1PREF Data Bus + _ C1IN- pin C1OUT pin C1OUTEN C1POL C1NREF The above block diagram demonstrates the effect of manipulating bits within CM1CON0 on the comparator module. 0.6VREF CM1CON0 C1PREF 1 C1OUTEN Comparator Output Enable Bit 1 = Output of Comparator is available internally only 0 = Output of Comparator is available internally and on the C1OUT pin

Comparator Block Diagram Comparator output (C1OUT) is available internally AND on C1OUT Pin C1IN+ pin C1PREF Data Bus + _ C1IN- pin C1OUT pin C1OUTEN C1POL C1NREF The above block diagram demonstrates the effect of manipulating bits within CM1CON0 on the comparator module. 0.6VREF CM1CON0 C1PREF C1OUTEN Comparator Output Enable Bit 1 = Output of Comparator is available internally only 0 = Output of Comparator is available internally and on the C1OUT pin

Comparator Wake-up on Change CM1CON0 1 1 C1OUT C1ON C1WU STATUS CWUF Input Condition C1PREF >C1NREF (C1OUT = 1) to Data Bus D Q EN The comparator can be configured to produce a wake-up from SLEEP if the C1OUT output value changes from a predefined value. To enable, the comparator wake-up on change bit CM1CON0<C1WU> needs to be cleared. The comparator also needs to be turned on by setting the CM1CON0<C1ON> bit. Before issuing the SLEEP instruction, the current value of C1OUT needs to be latched for reference. This can be accomplished by reading the CM1CON0 register such as moving CM1CON0 value into the Working Register. Once the SLEEP command is issued the PIC Microcontroller now enters Low-Power Mode. If the output of the comparator CM1CON0<C1OUT> changes from current latched value, the microcontroller will immediately RESET and begin program execution at the RESET vector. Remember, SFR registers are RESET to their default states as defined in the datasheet and GPR value are unknown. C1WU bit (CM1CON0<0>) + - C1PREF C1OUT pin C1NREF C1OUTEN C1POL

Comparator Wake-up on Change CM1CON0 1 1 C1OUT C1ON C1WU STATUS CWUF READ CM1CON0 READ CM1CON0 i.e. movf CM1CON0, W to Data Bus LAST C1OUT VALUE 1 D Q EN The comparator can be configured to produce a wake-up from SLEEP if the C1OUT output value changes from a predefined value. To enable, the comparator wake-up on change bit CM1CON0<C1WU> needs to be cleared. The comparator also needs to be turned on by setting the CM1CON0<C1ON> bit. Before issuing the SLEEP instruction, the current value of C1OUT needs to be latched for reference. This can be accomplished by reading the CM1CON0 register such as moving CM1CON0 value into the Working Register. Once the SLEEP command is issued the PIC Microcontroller now enters Low-Power Mode. If the output of the comparator CM1CON0<C1OUT> changes from current latched value, the microcontroller will immediately RESET and begin program execution at the RESET vector. Remember, SFR registers are RESET to their default states as defined in the datasheet and GPR value are unknown. + - C1PREF READ CM1CON0 C1OUT pin C1NREF C1OUTEN C1POL

Comparator Wake-up on Change CM1CON0 1 1 C1OUT C1ON C1WU STATUS CWUF to Data Bus Issue SLEEP instruction LAST C1OUT VALUE 1 D Q EN The comparator can be configured to produce a wake-up from SLEEP if the C1OUT output value changes from a predefined value. To enable, the comparator wake-up on change bit CM1CON0<C1WU> needs to be cleared. The comparator also needs to be turned on by setting the CM1CON0<C1ON> bit. Before issuing the SLEEP instruction, the current value of C1OUT needs to be latched for reference. This can be accomplished by reading the CM1CON0 register such as moving CM1CON0 value into the Working Register. Once the SLEEP command is issued the PIC Microcontroller now enters Low-Power Mode. If the output of the comparator CM1CON0<C1OUT> changes from current latched value, the microcontroller will immediately RESET and begin program execution at the RESET vector. Remember, SFR registers are RESET to their default states as defined in the datasheet and GPR value are unknown. + - C1PREF C1OUT pin C1NREF C1OUTEN C1POL

Comparator Wake-up on Change CM1CON0 1 C1OUT C1ON C1WU STATUS CWUF Input Condition changes: C1PREF <C1NREF (C1OUT = 0) to Data Bus LAST C1OUT VALUE 1 D Q EN The comparator can be configured to produce a wake-up from SLEEP if the C1OUT output value changes from a predefined value. To enable, the comparator wake-up on change bit CM1CON0<C1WU> needs to be cleared. The comparator also needs to be turned on by setting the CM1CON0<C1ON> bit. Before issuing the SLEEP instruction, the current value of C1OUT needs to be latched for reference. This can be accomplished by reading the CM1CON0 register such as moving CM1CON0 value into the Working Register. Once the SLEEP command is issued the PIC Microcontroller now enters Low-Power Mode. If the output of the comparator CM1CON0<C1OUT> changes from current latched value, the microcontroller will immediately RESET and begin program execution at the RESET vector. Remember, SFR registers are RESET to their default states as defined in the datasheet and GPR value are unknown. C1WU bit (CM1CON0<0>) + - C1PREF C1OUT pin C1NREF C1OUTEN C1POL

Comparator Wake-up on Change CM1CON0 1 1 C1OUT C1ON C1WU STATUS 1 CWUF Baseline PIC wakes, RESETs and begins Code execution at the RESET Vector to Data Bus LAST C1OUT VALUE 1 D Q EN CWUF bit STATUS<6> The comparator can be configured to produce a wake-up from SLEEP if the C1OUT output value changes from a predefined value. To enable, the comparator wake-up on change bit CM1CON0<C1WU> needs to be cleared. The comparator also needs to be turned on by setting the CM1CON0<C1ON> bit. Before issuing the SLEEP instruction, the current value of C1OUT needs to be latched for reference. This can be accomplished by reading the CM1CON0 register such as moving CM1CON0 value into the Working Register. Once the SLEEP command is issued the PIC Microcontroller now enters Low-Power Mode. If the output of the comparator CM1CON0<C1OUT> changes from current latched value, the microcontroller will immediately RESET and begin program execution at the RESET vector. Remember, SFR registers are RESET to their default states as defined in the datasheet and GPR value are unknown. C1WU bit (CM1CON0<0>) + - C1PREF READ CM1CON0 C1OUT pin C1NREF C1OUTEN C1POL

Comparator as TMR0 Clock Source CM1CON0 1 C1T0CS TIMER0 Module configured as a counter + - C1IN+ TMR0 C1OUT 1 1 1 1 C1IN- Finally, the comparator can be used as the clock source for the Timer0 module. TMR0 can then be incremented based on the C1OUT result of a comparison on the reference inputs.

Summary

Basic components of the Baseline PIC Microcontroller Architecture Course Summary Basic components of the Baseline PIC Microcontroller Architecture Special Features PIC12F510 Peripherals Input/Output Port Timer 0 Analog-to-Digital Converter Comparator

Resources Visit www.microchip.com for: 24/7 technical support www.microchip.com/com Visit www.microchip.com for: 24/7 technical support Application Notes Web Seminars Code examples Datasheets and Much More!

Questions?

Thank You!

LEGAL NOTICE SOFTWARE: You may use Microchip software exclusively with Microchip products. Further, use of Microchip software is subject to the copyright notices, disclaimers, and any license terms accompanying such software, whether set forth at the install of each program or posted in a header or text file. Notwithstanding the above, certain components of software offered by Microchip and 3rd parties may be covered by “open source” software licenses – which include licenses that require that the distributor make the software available in source code format. To the extent required by such open source software licenses, the terms of such license will govern. NOTICE & DISCLAIMER: These materials and accompanying information (including, for example, any software, and references to 3rd party companies and 3rd party websites) are for informational purposes only and provided “AS IS.” Microchip assumes no responsibility for statements made by 3rd party companies, or materials or information that such 3rd parties may provide. MICROCHIP DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING ANY IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY DIRECT OR INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND RELATED TO THESE MATERIALS OR ACCOMPANYING INFORMATION PROVIDED TO YOU BY MICROCHIP OR OTHER THIRD PARTIES, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBLITY OF SUCH DAMAGES OR THE DAMAGES ARE FORESEEABLE. PLEASE BE AWARE THAT IMPLEMENTATION OF INTELLECTUAL PROPERTY PRESENTED HERE MAY REQUIRE A LICENSE FROM THIRD PARTIES. TRADEMARKS: The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In‑Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, All Rights Reserved.