VDD M2 M1 Vbb Vin CL RL Vo VDD Vo Vb2

Slides:



Advertisements
Similar presentations
Lecture 4 Operational Amplifiers—Non-ideal behavior
Advertisements

Differential Amplifiers
1 EE 501 Fall 2009 Design Project 1 Fully differential multi-stage CMOS Op Amp with Common Mode Feedback and Compensation for high GB.
CMOS AMPLIFIERS Simple Inverting Amplifier Differential Amplifiers Cascode Amplifier Output Amplifiers Summary.
CMOS AMPLIFIERS Simple Inverting Amplifier Differential Amplifiers Cascode Amplifier Output Amplifiers Summary.
2. CMOS Op-amp설계 (1).
Prepared by PATEL DEEP J. ENROLL. NO PATEL JAINIL K. ENROLL.NO PATEL ASHISH. ENROLL.NO PATEL APURV ENROLL.NO
TECHNIQUES OF DC CIRCUIT ANALYSIS: SKEE 1023
Recall Last Lecture Biasing of BJT Applications of BJT
Recall Last Lecture Biasing of BJT Three types of biasing
Open book, open notes, bring a calculator
Recall Last Lecture Biasing of BJT Three types of biasing
FET Amplifier Circuits Analysis
ECE 3302 Fundamentals of Electrical Engineering
Recall Lecture 17 MOSFET DC Analysis
COMMON-GATE AMPLIFIER
Recall Last Lecture Introduction to BJT Amplifier
ANALOGUE ELECTRONICS I
Recall Lecture 14 Introduction to BJT Amplifier
Recall Lecture 17 MOSFET DC Analysis
Discussion #12 –Exam 1 Review
Design: architecture selection plus biasing/sizing
Recall Lecture 17 MOSFET DC Analysis
Voltage doubler for gate overdrive
TECHNIQUES OF DC CIRCUIT ANALYSIS: SKEE 1023

VDD M3 M1 Vbb Vin CL Rb Vo VDD Vo Vb3
CASCODE AMPLIFIER.
Last time Reviewed 4 devices in CMOS Transistors: main device
Fully differential op amps
vs vb cc VDD M9 M12 M11 Iref M1 M2 vo vin- vin+= voQ = vo CL M3 M4 M13
Last time Small signal DC analysis Goal: Mainly use CS as example
Last time Large signal DC analysis Current mirror example
vs vb cc VDD VDD VDD M9 M12 M11 vo Iref M1 M2 vin vin+= voQ CL vf=vin

A general method for TF It’s systematic Uses Mason’s formula
OpAmp (OTA) Design The design process involves two distinct activities: Architecture Design Find an architecture already available and adapt it to present.
Lesson 3: op amp fundamentals and open loop applications
Basic BJT Small-Signal Model
M2 M1 Vbb Vin CL M4 M3 Vyy Vxx VDD VDD Vo<Vxx+|Vt3| flip up-down
Input common mode range drop
VDD VDD VDD M2 M2 Iref vo+ vo- CL CL M1 M1 VoQ Voc vin- vin+ – + 2*M1.
Recall Last Lecture Introduction to BJT Amplifier
M2 M1 Vbb Vin CL M4 M3 Vyy Vxx VDD VDD Vo<Vxx+|Vt3| flip up-down
VDD VDD Vo<VG6+|Vt6| =VDD - |Vtp| - 2Veff M7 M5 M8 M6 vo
For a differential amplifer: vin+=vic+vid/2, vin-=vic-vid/2
Last time Reviewed 4 devices in CMOS Transistors: main device
Miller equivalent circuit
Recall Last Lecture Introduction to BJT Amplifier
Basic current mirror Small signal: Rin = 1/(gm1+gds1)  1/gm1
M2 M1 Vbb Vin CL M4 M3 Vyy Vxx VDD VDD Vo<Vxx+|Vt3| flip up-down
Recall Lecture 17 MOSFET DC Analysis
Types of Amplifiers Common source, input pairs, are transconductance
Input common mode range
Common source output stage:
Differential Amplifier
vs vb cc VDD VDD VDD M9 M12 M11 vo Iref M1 M2 vin vin+= voQ CL vf=vin
Folded cascode stage: summing current and convert to voltage
Rail-to-rail Input Stage
Differential Amplifier
VDD Vin+ CL Vin- Vb3 folded cascode amp Vb2 Vb1 Vb4 Vb5.
A general method for TF It’s systematic Uses Mason’s formula
VDD VDD VDD M2 M2 Iref vo+ vo- CL CL M1 M1 VoQ Voc vin- vin+ – + 2*M1.
Common-Collector (Emitter-Follower) Amplifier
Common-Collector (Emitter-Follower) Amplifier
Recall Last Lecture Introduction to BJT Amplifier
Common-Collector (Emitter-Follower) Amplifier
Vout Vin 10V ID 500W Vout IL RL 5 1kW Vout VB ID 1kW Vout 1V 1kW VG.
Recall Last Lecture Introduction to BJT Amplifier
Common-Collector Amplifier
Presentation transcript:

VDD M2 M1 Vbb Vin CL RL Vo VDD Vo Vb2 Both share the same small signal model. gm2 may include gmb2, rds1 may include rp-source Cs2 include all caps at S2

vg1/vin =1/(1+sRsaCgs1) KCL at Vo: KCL at Vs2:

ro  rds1*Av2 || RL Av(0)  - gm1ro p1 = - w-3dB = -1/roCout GBW = gm1/Cout z1 = +gm1/Cgd1 p2  -1/{(rds1|| rincg)Cs2} p3  -1/RsaCgs1

Slew rate: the maximum rate at which a node voltage can change. SR+: max ↑; SR-: max ↓ To compute: find max current, divide by total cap VDD VDD M2 vo 10m CL M1 Vin Positive slew rate SR+ = I2Q/CLtot Negative slew rate SR- = (I1max-I2Q)/CLtot I1max can be very large when Vin is very large. So, SR- is unknown but can be large. From a desired SR+, we need I2Q = SR+ * CLtot To accommodate parasitics: I2Q = SR+ * 1.2CLtot