Test Fixture (Testbench)

Slides:



Advertisements
Similar presentations
VERILOG: Synthesis - Combinational Logic Combination logic function can be expressed as: logic_output(t) = f(logic_inputs(t)) Rules Avoid technology dependent.
Advertisements

Stimulus and Response. Simple Stimulus Verifying the Output Self-Checking Testbenches Complex Stimulus Complex Response Predicting the Output.
Chapter 15:Introduction to Verilog Testbenches Objectives In this section,you will learn about designing a testbench: Creating clocks Including files Strategic.
Simulation executable (simv)
Synchronous Sequential Logic
Combinational Logic.
Table 7.1 Verilog Operators.
Hardware Description Language (HDL)
Verilog. 2 Behavioral Description initial:  is executed once at the beginning. always:  is repeated until the end of simulation.
OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.
ELEN 468 Lecture 91 ELEN 468 Advanced Logic Design Lecture 9 Behavioral Descriptions III.
Verilog Sequential Circuits Ibrahim Korpeoglu. Verilog can be used to describe storage elements and sequential circuits as well. So far continuous assignment.
ELEN 468 Lecture 161 ELEN 468 Advanced Logic Design Lecture 16 Synthesis of Language Construct II.
Verilog HDL (Behavioral Modeling) Bilal Saqib. Behavioral Modeling.
Silicon Programming--Intro. to HDLs1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities.
Advanced Verilog EECS 270 v10/23/06.
Verilog Intro: Part 2. Procedural Blocks There are two types of procedural blocks in Verilog. – initial for single-pass behavior : initial blocks execute.
Today’s Lecture Process model –initial & always statements Assignments –Continuous & procedural assignments Timing Control System tasks.
RTL Coding tips Lecture 7,8 Prepared by: Engr. Qazi Zia, Assistant Professor EED, COMSATS Attock.
Advanced FPGA Based System Design Lecture-9 & 10 VHDL Sequential Code By: Dr Imtiaz Hussain 1.
Week Four Design & Simulation Example slides. Agenda Review the tiny example (Minako “logic”)from last week – look at the detailed static timing report.
SoC Verification HW #2 TA: Wei-Ting Tu Assignment: 04/12/06
ECE 551 Digital System Design & Synthesis Fall 2011 Midterm Exam Overview.
1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.
1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.
Register Transfer Level & Design with ASM
1 CSE-308 Digital System Design (DSD) N-W.F.P. University of Engineering & Technology, Peshawar.
Anurag Dwivedi. Basic Block - Gates Gates -> Flip Flops.
Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Topics VHDL register-transfer modeling: –basics using traffic light controller; –synthesis.
Behavioral Modelling - 1. Verilog Behavioral Modelling Behavioral Models represent functionality of the digital hardware. It describes how the circuit.
George Mason University Simple Testbenches ECE 545 Lecture 4.
Verilog A Hardware Description Language (HDL ) is a machine readable and human readable language for describing hardware. Verilog and VHDL are HDLs.
VHDL – Behavioral Modeling and Registered Elements ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering Dr.
M.Mohajjel. Structured Procedures Two basic structured procedure statements always initial All behavioral statements appear only inside these blocks Each.
 A test bench is an HDL program used for applying stimulus to an HDL design in order to test it and observe its response during simulation.  In addition.
OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.
SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapters 4 – Part4: Verilog – Part 2.
1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.
EMT 351/4 DIGITAL IC DESIGN Verilog Behavioral Modeling  Constructs for Activity Flow Control  Task & Function  System Tasks for Timing Checks.
Structural Description
Overview Logistics Last lecture Today HW5 due today
Supplement on Verilog FF circuit examples
Timing and Verification
Verilog Introduction Fall
Testbenches HDL that tests another module: device under test (dut)
‘if-else’ & ‘case’ Statements
Timing Model Start Simulation Delay Update Signals Execute Processes
Verilog-HDL-3 by Dr. Amin Danial Asham.
ECE 448 Lab 1a Developing Effective Testbenches
Testbenches HDL that tests another module: device under test (dut)
RTL Design Methodology
Introduction to Verilog
SYNTHESIS OF SEQUENTIAL LOGIC
Developing More Advanced Testbenches
FSM MODELING MOORE FSM MELAY FSM. Introduction to DIGITAL CIRCUITS MODELING & VERIFICATION using VERILOG [Part-2]
SystemVerilog Implementation of GCD
Lecture 3 Simulation and Testbench
Chapter 4: Behavioral Modeling
The Verilog Hardware Description Language
Dr. Tassadaq Hussain Introduction to Verilog – Part-3 Expressing Sequential Circuits and FSM.
The Verilog Hardware Description Language
RTL Design Methodology
The Verilog Hardware Description Language
ECE 545 Lecture 5 Simple Testbenches.
RTL Design Methodology Transition from Pseudocode & Interface
Introduction to Digital IC Design
Introduction to Verilog – Part-2 Procedural Statements
Sequntial-Circuit Building Blocks
COE 202 Introduction to Verilog
(Simple Testbenches & Arithmetic Operations)
Presentation transcript:

Test Fixture (Testbench) Much more like programming! =:0 Generate clock and reset Apply stimulus Check results (optional) Terminate simulation (recommended) Add test fixture as a “simulation source” under “Add Sources”

// Instantiate the Unit Under Test (UUT) top uut ( .clk(clk), `timescale 1ns / 1ps module tb; // Inputs logic clk; logic rst; logic load; logic [7:0] din; // Outputs logic [7:0] gcd_rslt; logic done; // Instantiate the Unit Under Test (UUT) top uut ( .clk(clk), .rst(rst), .load(load), .din(din), .gcd_rslt(gcd_rslt), .done(done) ); [...] Note: The tb module has no inputs or outputs on its interface Only a single component instantiation Internal signals correspond to UUT interface reg type indicates signals that will be generated internally by the testbench via procedural assigns time scale means the unit multiplier for delays is ns with a resolution of 1 ps, so you could delay 1.001 ns.

Clock Generation [...] parameter CLK_PRD = 100; // 10 MHz clock parameter HOLD_TIME = (CLK_PRD*0.3); initial begin clk <= 0; forever #(CLK_PRD/2) clk = ~clk; end Define the clock period and hold time requirements. The “initial” keyword identifies a single-pass behavior that will only “execute” once. In this case it generates a periodic waveform. Forever loop with a single statement The “#” is a delay construct that allows simulation time to advance before execution continues Basically, after specified delay (in nsec), exectute the statement. Note the mix of blocking and non-blocking. Not recommended for synthesis, only testbenches Initial assignment with non-blocking is to allow other initial blocks to evaluate at start-up (I think!)

Reset and Stimulus Alignment initial begin // Initialize Inputs rst = 0; load = 0; din = 8'bx; // Wait 100 ns for global reset to finish #100; // Add stimulus here @(posedge clk); // align with clock edge #HOLD_TIME; // offset a hold time repeat(2) #CLK_PRD; // Now only wait integer clock periods rst = 1; #CLK_PRD; repeat(2) #CLK_PRD; [...] FPGA include a global set/reset after configuration that is modeled in post-implementation simulation, so you want your testbench to wait. @ is an event control operator with a sensitivity list Followed by #hold sets stimulus at a hold time after rising edge. din set to all “x” clock twice to allow X to propagate, then reset for 1 cc, then clock two more cycles to make sure it stays initialized

Stimulus and Done Check [...] load = 1; #CLK_PRD; load = 0; din = 8'd27; #CLK_PRD; din = 8'd18; #CLK_PRD; din = 8'bx; #CLK_PRD; begin : run_loop forever begin @(posedge clk); if (done) disable run_loop; end end // run_loop $finish; endmodule din set back to “x” Named forever loop to allow break on done $finish is a system task that returns control to the simulator Will run forever if done never asserted, causing simulator to appear to lock up Better is to include a max sim constraint using a single cycle block

Simulation Termination parameter MAX_SIM_TIME = (100*CLK_PRD); initial #(MAX_SIM_TIME) $finish; Allows a maximum simulation time of 100 clock cycles