Memory Systems CH008.

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Presentation transcript:

Memory Systems CH008

Figure 8.1 The memory interface Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved. Figure 8.2 Diverging processor and memory performance. Adapted with permission from Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 5th ed., Morgan Kaufmann, 2011. Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.3 A typical memory hierarchy Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved. Figure 8.4 Memory hierarchy components, with typical characteristics in 2015 Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.5 Mapping of main memory to a direct mapped cache Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved. Figure 8.6 Cache fields for address 0xFFFFFFE4 when mapping to the cache in Figure 8.5 Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.7 Direct mapped cache with 8 sets Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.8 Direct mapped cache contents Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.9 Two-way set associative cache Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.10 Two-way set associative cache contents Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.11 Eight-block fully associative cache Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved. Figure 8.12 Direct mapped cache with two sets and a four-word block size Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved. Figure 8.13 Cache fields for address 0x8000009C when mapping to the cache of Figure 8.12 Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.14 Cache contents with a block size b of four words Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.15 Two-way associative cache with LRU replacement Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.16 Memory hierarchy with two levels of cache Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved. Figure 8.17 Miss rate versus cache size and associativity on SPEC2000 benchmark. (Adapted with permission from Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 5th ed., Morgan Kaufmann, 2012.) Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved. Figure 8.18 Miss rate versus block size and cache size on SPEC92 benchmark. (Adapted with permission from Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 5th ed., Morgan Kaufmann, 2012.) Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved. Figure 8.19 Hard disk Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.20 Virtual and physical pages Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.21 Physical and virtual pages Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.22 Translation from virtual address to physical address Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.23 The page table for Figure 8.21 Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.24 Address translation using the page table Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.25 Address translation using a two-entry TLB Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.26 Hierarchical page tables Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.27 Address translation using a two-level page table Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.28 Building blocks Copyright © 2016 Elsevier Ltd. All rights reserved.

Figure 8.29 Computer system Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved.

Copyright © 2016 Elsevier Ltd. All rights reserved. Fig u08-01 Copyright © 2016 Elsevier Ltd. All rights reserved.