Day 20: October 18, 2013 Ratioed Logic ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 20: October 18, 2013 Ratioed Logic Penn ESE370 Fall2013 -- DeHon

Previously Restoration and Noise Margins CMOS Gates Drive rail-to-rail Only one transistor turned on in steady state Only subthreshold current in steady state Penn ESE370 Fall2013 -- DeHon

Today Ratioed Gates Break all the rules… (nice properties) Correctness Not rail-to-rail, steady-state-current… Correctness Performance Power Implications Penn ESE370 Fall2013 -- DeHon

Note on what about to see Not clear win Should be able to analyze Chance to exercise analysis Kind of thing you want to be able to analyze Pattern should recognize Stepping stone to more interesting things to come… Penn ESE370 Fall2013 -- DeHon

Idea Building both pull-up and pull-down can be expensive – many gates Seems wasteful to build logic function twice Once in pullup, once in pulldown Large capacitance Penn ESE370 Fall2013 -- DeHon

Idea Maybe only need to build one Build NFET pulldown Exploit high N mobility traditional Penn ESE370 Fall2013 -- DeHon

Ratioed Inverter Does this work? Vout for Vin=0V ? Vout for Vin=1V ? WP=1 WN=1 Penn ESE370 Fall2013 -- DeHon

Ratioed Inverter Does this work? Vout for Vin=0V ? Vout for Vin=1V ? WP=1 WN=1 Penn ESE370 Fall2013 -- DeHon

Ratioed Inverter Wn=1 Penn ESE370 Fall2013 -- DeHon

Ratioed Inverter How do we need to size N to make it work? WP=1 Penn ESE370 Fall2013 -- DeHon

DC Transfer Function Penn ESE370 Fall2013 -- DeHon

Ratioed Inverter How do we need to size P to make it work? WN=1 Penn ESE370 Fall2013 -- DeHon

P vs. N Conclude: still prefer N to P for ratioed logic ….at least for now Penn ESE370 Fall2013 -- DeHon

Worst-Case Output Drive Strength? Rdrive? WP=1 Penn ESE370 Fall2013 -- DeHon

Noise Margin Tradeoff What is impact of increasing (reducing) noise margin? Penn ESE370 Fall2013 -- DeHon

Ratioed Inverter Sizing Penn ESE370 Fall2013 -- DeHon

Ratioed Inverter Sizing What causes knee in curve at high end? Penn ESE370 Fall2013 -- DeHon

S D Non-VSAT Equations Penn ESE370 Fall2013 -- DeHon

Non-VSAT Equations P looks roughly like current source D Non-VSAT Equations P looks roughly like current source Must Match current with N Determine Vds How does Wn effect Vds? Penn ESE370 Fall2013 -- DeHon

Non-VSAT Equations Once drop into linear region Isdp constant = Idsn Vds < Vgs-Vt Constant = (Vgs-Vt) Vds Vds α 1/(Vgs-Vt) Penn ESE370 Fall2013 -- DeHon

Size for R0/2 drive? How do we size for R0/2 drive? Penn ESE370 Fall2013 -- DeHon

Compare Static CMOS For Rdrive=R0/2 inverter Total Transistor Width? Input capacitance load? Penn ESE370 Fall2013 -- DeHon

Power? Istatic ? Output high? Output low? Ileak Ipmos_on Vdd/(R0/2) -- for our sample case Penn ESE370 Fall2013 -- DeHon

Power Ptot ≈ a(½Cload+Csc)V2f +PlowV2/Rpon +(1-Plow)VI’s(W/L)e-Vt/(nkT/q) Penn ESE370 Fall2013 -- DeHon

How size for R0/2 drive? Penn ESE370 Fall2013 -- DeHon

How size for R0/2 drive? Penn ESE370 Fall2013 -- DeHon

How size for R0/2 drive? How size K-input nor? Penn ESE370 Fall2013 -- DeHon

When better than CMOS nor-k? Better = smaller, lower input capacitance Penn ESE370 Fall2013 -- DeHon

Which Implementation is faster in ratioed logic? Penn ESE370 Fall2013 -- DeHon

Illustrates Preferred gate changes Penn ESE370 Fall2013 -- DeHon

Ideas There are other logic disciplines We have the tools to analyze Ratioed Logic Tradeoff noise margin for Reduced area? Capacitive load? Dissipates static power in one mode Penn ESE370 Fall2013 -- DeHon

Admin Project Should have read it Build and simulated baseline over weekend Start list of optimizations to try If don’t have list talk with Spencer or André during office hours Penn ESE370 Fall2013 -- DeHon