A Play Lab. 2 Task 8 Core Timer Interrupts Acted by the Human Microcontroller Ensemble from ENCM415

Unanswered questions What does “volatile” mean? Why will “optimized code” probably not work for interrupt service routines if the keyword volatile is not used? How do you tell C++ that this function is an ISR and not a standard function? Why do you need to tell C++ that this function is an ISR and not a standard function? What is the difference (in coding) between an ISR and a standard function? How does an interupt get latched, why and where? Why do I have to tell the timer that the interrupt has been serviced, and how do I do it? Task 2 – file 2 (C++ or ASM) extern volatile int foo_flag; Tell “C++” that I am not a function but I am an ISR – interrupt service routine ???How declare?? ISR_count( ) { foo_flag--; Tell the timer that the interrupt has been serviced } 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Timers available on Blackfin Watchdog timer – Hardware Reference 15-49 Core timer – Hardware Reference 15-45 General purpose timers 15-1 Pulse Width Modulation Pulse Width Count and Capture External Event Application of timers to provide code safety and improved version of UseFixedTimeASM( ) Introduction to timer interrupts 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Act 1 – The MAIN task number_of_interrupts should have been a VOLATILE Key for exam – working by luck does not count Works – by luck – because compiled with “DEFAULT MODE” where all variables are treated as “volatile” Would not work in “RELEASE MODE” where “unneeded” or “unused” code is removed 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Main.cpp as assembly code Debug option Number of interrupts checked In loop 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Main.cpp as assembly code Release option Number of interrupts NOT checked In loop 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Main.cpp as assembly code Release option “Volatile” used 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

How NOT to add a C++ interrupt service routine Standard return From subroutine 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

How NOT to add a C++ interrupt service routine Since ISR’s can be caused to happen at “ANY” time by external signals you can’t code parameter passing or parameter returning 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

A proper C++ ISR Save and recover of all registers (volatile and nonvolatile) After recovering all registers we need to RTI -- return from interrupt NOT – repeat NOT return from subroutine Using P0 =[FP + 4]; UNLINK etc. FP? ASTAT? Is saving all registers needed? Would saving R and P1 beenough? 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Players need to audition for the part of the Core Timer Registers Core Timer Scale Register TSCALE Requires ability to communicate with TCOUNT register Core Timer Count Register TCOUNT Requires ability to count backwards in steps of TSCALE + 1 Core Timer Period Register TPERIOD Core Time Control Register TCNTL Leadership role – has ability to put timer into low power mode, disable timer, enable auto reload feature which place TPERIOD into TCOUNT whenever TCOUNT reaches zero (causing an interrupts). Has a “sticky bit” 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Core Timer Action You set Core timer register TSCALE to 0 (decrement by 0 + 1) You set register TPERIOD to 0x2000 You set register TCOUNT to 0x4000 You enable timer using control register TCNTL TCOUNT is decreased by 1 until it reaches 0 (0x4000 system clock ticks) When TCOUNT reaches 1, interrupt is caused and TCOUNT is reloaded with TPERIOD (0x2000) – counts down again 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

The play is about to start 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Now we need to add the actors Main( ) -- 2 actors Doing something Number_Interrupts ISR routine – 1 actor 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

The play starts The main program and ISR operation will now be demonstrated The narrator will now “Build ALL”, and then DEBUG | RUN WHAT ELSE IS NEEDED MAKE THE ISR WORK? 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Now we need to add the actors Timer – 4 parts Core Timer Scale Register TSCALE Core Timer Count Register TCOUNT Core Timer Period Register TPERIOD Core Time Control Register TCNTL 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Starting the play Attempt 2 Main( ) -- 2 actors Doing something Number_Interrupts ISR routine – 1 actor Me_ISR); 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Important system registers Core interrupt mask register IMASK Must be super person with ability to stop / start all interrupts in the world Controls IVTMR interrupt bit Core Interrupt Latch register ILAT Has ability to remember if interrupt has occurred (been latched) but is being ignored – bits set from one to zero when interrupt has been accepted “recognized” by the processor Core Interrupt Pending Register IPEND Read but not written – indicates that interrupt is active (recognized) or nested 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Now we need to add the actors Timer – 4 parts Core Timer Scale Register TSCALE Core Timer Count Register TCOUNT Core Timer Period Register TPERIOD Core Time Control Register TCNTL CORE SYSTEM REGISTERS – 1 person with many hands Core interrupt mask register IMASK Core Interrupt Latch register ILAT Core Interrupt Pending Register IPEND 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

Real demonstration Main( ) -- 2 actors Doing something Number_Interrupts ISR routine – 1 actor Timer registers – 4 actors Core registers – 1 actor Me_ISR); 1/13/2019 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada