State Machine Design with an HDL A methodology that works for documenting the design, simulation and verification of the design, and synthesis for FPGA, or a custom ASIC generated using synthesis. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU Lecture overview State machine basics HDL methodology State machine example 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU State Machine Basics In basic digital designs there are two fundamental ways that state machines are implemented Mealy Machine Outputs are a function of the current state and the inputs 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU State Machine Basics Moore Machine Outputs are a function of the current state only 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU Some interesting info Mealy machine is names after George H. Mealy who presented a paper in 1955, “A Method for Synthesizing Sequential Circuits.” Formal definition – A Mealy machine is a 6-tuple, A finite set of states A start state (initial state) A finite set called the input alphabet A finite set called the output alphabet A transition function (T: S x S S) mapping pairs of a state and an input symbol to the corresponding next state. An output function (G : S x S D) mapping pairs of a state and an input symbol to a corresponding output symbol. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU and Moore machine is names after Edward F. Moore who presented a paper in 1956, “Gedanken-experments on Sequential Machines.” Formal Definition: A finite set of states A start state (initial state) A finite set called the input alphabet A finite set called the output alphabet A transition function (T: S x S S) mapping a state and the input alphabet to the next state. An output function (G : S D) mapping each state to the output alphabet. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU HDL code Coding a state machine in an HDL Can simply implement an algorithm Documents poorly Cannot be synthesized (possibly but less than optimal result) Can code for a Mealy or Moore machine in a single process Synthesis results are unpredictable Can follow a structured style Documents very well Synthesizes very well and results are predictable Simulation of the three possibilities is ~ the same 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU The coding style The style applies to any HDL – VHDL, Verilog, System Verilog, and System C Documents well Easily maintainable – excellent during development as changes are easily made Style maps to physical logic – using this style can predict the number of state elements (~) that should be produced by synthesis All three styles on the last slide simulate equally well, but this style also synthesizes well. Works in XILINX and Altera tools. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Style guide for sequential circuits Use a process to describe the next state logic, often in a case statement used for determination of the next state. Will see this in the example. Use a process to represent the latching/loading of the calculated next_state such that it becomes the current_state. This is the only process that generates sequential elements (F/Fs). The other processes represent combinational logic. Can use a template. Use a third process to represent the generation of the outputs from the current state and possibly the inputs. This process will have as its inputs, the current state and, depending on the type of state machine, the state machine inputs. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU An example The T-Bird tail light problem The turn signal indicator had a light sequence on each lamp. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
State machine description State Diagram and Transition table Output is associated with state – a Moore machine 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU Design with HDL You still start with a state diagram You may or may not generate a transition table Will now look at the code Where to start – THE INTERFACE What are the inputs and the outputs? 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU The Entity Inputs are a signal for Right turn signal Left turn signal Hazard Clock Outputs are the signals for the lights lc, lb, la rc, rb, ra 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU The Entity Inputs are a signal for Right turn signal Left turn signal Hazard Clock Outputs are the signals for the lights lc, lb, la rc, rb, ra 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU The architecture Will use 3 processes Start of architecture and the process to specify the F/Fs is given here. Use of a state_type allow the coding to also document the design. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Notes on start of architecture Signal declaration for the state machine state First declare an enumeration type that has an element for each state of the state machine Here- idle, l1,l2,l3, r1,r2,r3, lr3 Then declare signals state and next_state to be of this type. These represent the current state and the calculated next state. An aside: you can count the number of elements in this type to see that number of states and predict the number of F/Fs the state machine requires. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU The F/F process Have a process that specifies latching the next_state into the signal state. This process will synthesize into F/Fs Process specifies that this happens on the clock edge. Note that state and next_state have an initial state of idle. Process will hold waiting for an edge on the clock signal clk 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU The next state process The second of the processes for the state machine. What is the next state given the current state and the state of the input signals Process can be of considerable size Continued on next slide 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU The next state process Continued Note that a case is used to switch to actions based on the current_state Then the value of the inputs directs the next_state for the state machine 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU The output process Use a separate process to specify the outputs In this case there is a specific set of outputs for each state. The outputs are only dependent on the state which makes this a Moore Machine 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Once you have state machine description Simulate it in a test suite to verify the design meets specifications. This is the HDL topic of verification Then can synthesize the design to generate an FPGA implementation or use standard cells and generate the standard cells which can be sent to a place and route program for automatic generation of the circuit for a custom IC. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU If this is done What would you expect How many F/Fs??? For the example you would expect 3 FFs. Why? There are 8 states You could even ballpark the number of gates, but that is a bit much. 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU The synthesis result Note the number of F/Fs 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
The VHDL Style - summary 3 Processes One process for the F/Fs One process for the Next State Generation Breaks down nicely using a case state structure Documents the state transitions nicely and easy to maintain One process for the Output Generation from the state or from the state and current inputs 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Copyright 2006 - Joanne DeGroat, ECE, OSU The F/F process The form presented in the example is a simple edge triggered latch/F/F, in this case rising edge PROCESS BEGIN WAIT UNITL clk=‘1’ AND clk’event; state <= next_state; END PROCESS; 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
A more complete F/F specification -- Asynchronuous Preset and Clear PROCESS (clk,preset,clear,next_state) BEGIN -- active low preset and clear IF (preset = ‘0’) THEN state <= pr_state; --preset state ELSIF (clear = ‘0’) THEN state <= clr_state; --clear state ELSIF (clk = ‘1’ AND clk’event) THEN --rising edge state <= next_state; END IF; END PROCESS; 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU
Changing to Synchronous Reset/Clear -- Synchronous Preset (precedence) and Clear PROCESS (clk,preset,clear,next_state) BEGIN -- active low preset and clear IF (clk = ‘0’ AND clk’event) THEN –falling edge IF (preset = ‘0’) THEN state <= pr_state; --preset state ELSIF (clear = ‘0’) THEN state <= clr_state; --clear state ELSE state <= next_state; END IF; END PROCESS; 1/8/2007 - L20 Project Step 8 - Data Path Copyright 2006 - Joanne DeGroat, ECE, OSU