Common source output stage: Vxx M4 M7 When Vo1 goes low, Vo goes high. When M6 turns off, Vo goes to VDD. But M7 goes triode when Vo reaches VDD – Von7. But Vo can never goes to VSS even if Vo1=VDD! For Vo to go to VSS, M7 has to be turned off. Vyy M3 Vo Vo1 Vbb M2 M6 M1

Don’t do What about this? Vxx M4 M7 Vyy M3 Vbb M2 M6 M1 Unpredictable current in second stage

Second stage push pull: Monticelli style Vxx M4 M7 Vxx Vbn Vyy M3 Vbp Vbn Vbp Vzz Vbb M2 So, Vg6Q = Vzz This sets Id6Q. So, Vg7Q = Vxx This sets Id7Q. M6 M1 Requires: VDD-VSS > Vgs6+Vgs7+Vdssat_floating_CS + Vo1 swing D. M. Monticelli, “A quad CMOS single-supply Op Amp with rail-to-rail output swing,” IEEE J.Solid-State Circuits, no. 6, pp. 1026–34, Dec. 1986.

Floating CS do not change ro1 or DC gain The impedance looking down from Vo1+ is Rn To find impedance looking up from Vo1+, inject a test current i up. V’o1+ = i*Rp i_gdsn/p = (i - gmnvo1++gmpv’o1+) Vo1+=V’o1+ + i_gdsn/p /(gdsn + gdsp) Vo1+=i*Rp+(i - gmnvo1++gmpi*Rp) /(gdsn+gdsp) Vo1+(1+gmn /(gdsn+gdsp)) =i*{Rp[1+gmp/(gdsn+gdsp)] +1/(gdsn+gdsp)} Vo1+/i =Rp gmp/gmn gds4 Rp gds3 gm3vcp V’o1+ gmnvo1+ gdsn gdsp -gmpv’o1+ vo1+ gm2avcn +gmb2avcn gds2a Rn gds1 So, size them so that gmp ≈ gmn Note: gmn and gmp include possible body effects.

To the two gate terminals of M6 and M7, the two floating CS appears as a voltage source providing a voltage offset between the gates. The impedance seen by the two gate terminals can be calculated by: Rs = (Vgp – Vgn)/(current through the floating CS) = (Vgp – Vgn)/(gmp*Vgp – gmn*Vgn + (Vgp – Vgn)*(gdsn+gdsp)) ≈ 1/(gmp + gdsn+gdsp) ≈ 1/gmp The above assumed that the NMOS and PMOS are sized to have the same gm. Also, the calculation is only valid when both NMOS and PMOS are fully on and both in saturation. When Vo is experiencing large swings, these conditions are not met. And the voltage difference between the two gate terminals no longer remain constant.

HW: summarize the above discussion into a design procedure for given desired bias currents in output stage Io and the cascade stage Ic. Suppose a Iref is given. HW: find Vo swing range, if all transistors remain in saturation. Find io range if all transistors remain in saturation, where io = i7 – i6. When the floating current source transistors are allowed to go into triode but all other transistors need to remain in saturation, what is the io range?

Low Voltage Push-pull output Main goal: make Vo swing from Vss to Vdd. Equivalent to double the output stage gm, ↑gain, GB Make slew rate higher than Io/CL 1:M Io/M Io 1:M Make output Vebo small. When Vo1 swings, say by 2.1Vebo, ICL can be 10xIo! But quiescent Io depends on Vo1Q, and uncontrolled.

In order for the output transistors to have well defined quiescent current, we have to bias the circuit so that at Q, Vd12 = VgsnQ to establish correct quiescent current in nMOS. This must be through current mirror ratio. Problem: Vd12 is a high impedance node, small current mismatch in M10 and M6 leads to significant voltage change at vd12, which in turn changes the biasing current in the output stage. Solution: use feedback to stabilize common mode of Vd12. Vzz

Vzz Vd12 Vd11 Feedback to M4 or part of it Since Vd12 and Vd11 are normally nearly constant. We do not need to worry about the input range accommodation for this circuit. Size the circuit so that, when vid =0, Io remain near desired level over all process variations in M10 and M6.

Output quiescent current control by local CMFB. Vo1 CMFB 1:M Itail Io/M Io/M Io 1:M 1:1 match

Output quiescent current control by local CMFB. Vo1 CMFB 1:M Itail Io/M Io/M Io 1:M 1:1 match

Can passive CM detector be use?

M1a+M1b forms diff pair with M2 Vo1+/- swing is about +- 2.# * Vebo, or about +- 0.3 to 0.4 V, so M1a and M1b should have Veb about equal to 2*Vebo. Vb3 should be selected so that M12 is still in saturation when Vo1 drops to a little below Vthn-Vebo. The Veb of M12, M10, and the size of diode connected CMFB1 transistor should be such that M 10 is guaranteed to be in saturation. Note that there is only one high impedance node (Vo1 node) in this CMFB loop, hence the loop UGF can be made high and still maintain good stability.

Vo+ and Vo- also need common mode stabilization M17t and M21t are in triode M21t M17t M21 M17 M18 Vocmd M19 M15 R R C C M20 M16 Choose R to a couple times bigger than Ro Choose C to be near or a couple times larger than Cgs of CMFB circuit.

M:1 1:M Vxx Vxx M:1 1:M Vocmd R R C C

Why RC in common mode detector KCL at V: (V1 – V)/R + (V2 – V)/R = V * sCgs (V1 + V2)/R = V(sCgs + 2/R) V = (V1 + V2)/2 * 1/(1 + sRCgs/2) When |s| =|jw| << 2/RCgs, V ≈ (V1 + V2)/2 Otherwise V is not close to common mode To have CM detector work up to GB, R << 2/(2pGB*Cgs) V1 R V Cgs R V2

Why RC in common mode detector KCL at V: (V1 – V)(1/R +sC) + (V2 – V) (1/R +sC) = V * sCgs (V1 + V2) (1/R +sC) = V(sCgs + 2/R +2sC) V = (V1 + V2)/2 * (1 + sRC)/(1 + sRC + sRCgs/2) As long as Cgs/2 < C, at all freq: V ≈ (V1 + V2)/2 V1 R C V Cgs C R V2 Hence, the RC network acts as a better CM detector

Why CMBF to M17t instead of first stage: For CM behavior, assume DM=0. Vo1+=Vo1-, and Vo+=Vo-=Vocm. Without CMFB effect, at Q, Vo+ will be equal to Vg, which may be far below desired Vocm level. With CMFB connected, the feedback effect will drive Vo1 so as to move Vo+ up to the desired Vocm level. Since Vo1+ and Vo1- have a competing action on Vo+, it may take quite bit Vo1 movement to achieve the desired Vo+ movement, causing the biasing current in the second stage to be much larger than what is intended. Vo1+ Vo1- Vo+ Vg

Compensation for diff signal path’s closed-loop stability Vxx M4 M7 M7 Vyy M3 M3 CC CC Vbb M2 M2 M6 M6 M1 Vzz M1 Standard lead compensation

At relatively low frequency: Because of gain from Vo1 to Vo, small signal Vo1 is much smaller than small signal Vo. Small signal current in compensation network is approximately Vo/(1/gmz+1/sCc). This current is injected to the Vo1 node. Alternatively, a similar current can be injected: Impedance looking into a cascode node is about 1/gm Connecting Cc to a cascode node generates a current of the form Vo/(1/gm +1/sCc) Because the base transistor is a current source, this small signal current goes to the Vo1 node Even at high frequency, the current form is still valid.

Alternative compensation: Ahuja Vxx M4 M7 M7 Vyy M3 M3 CC CC Vbb M2 M2 M6 M6 M1 Vzz M1 Also called indirect compensation.

In the Cc+Mz connection, Bias voltage of Mz can be matched to track bias voltage of M6  robustness to process and temperature variations Size of Mz can be parameter scanned so as to place zero to cancel the secondary pole of the amplifier In the Cc to cascode connection, Bias voltage can still be derived using current mirrors from a single current source,  still have process and temperature tracking But size of cascode transistor is determined based on folded cascode stage design Cannot arbitrarily choose its size without considerations for output impedance at Vo1, gain of op amp, and so on.

With Vicm at “sweet spot”, sweep Vin near Vicm with very fine steps (uV) Vo+ Vo- Vicm Vin Vin d(Vo+-Vo-) dVin Vo+-Vo- Vin