Case Study Low-Power Wireless Networks Jay Bruso Mike Matranga

Overview Project Status Architecture Review Gate Array Design Test Results Modeling Predicted Results Applications Summary

Project Status Completed proto-type model Power Analysis 2.4 GHz band 250, 10 Kbps data rate Packet rate (1 Hz, 10 Hz, or 100 Hz) Packet length (variable) Encoded using LFSR Power Analysis Completed power measurements Developed model for other scenarios

Architecture A DLL Manages Data Reception CPU awoken at start of message CPU processes data until EOM detected CPU returns to low-power sleep mode at EOM

Architecture B PL Manages Data Reception CPLD manages interface to transceiver CPLD processes data until EOM detected CPLD awakes CPU from sleep mode Reads stored message from SRAM and sends to DLL

Architecture Modification Addition of SRAM Original plan was to store entire received message within CPLD Problem … CPLD not large enough XCR3512 contains only 512 FF (64 bytes) Problem solved by use of external SRAM Allows for larger messages CPLD memory only used for control logic

CPLD Design Simple State Machine 2 Operation Modes Length based message framing Character based message framing Length based processing Stores first byte received and interprets as length Continues acquiring data until length met Character based processing Waits until SOM detected Stores data until EOM detected

CPLD State Machine

Test Results, Case 1-A

Test Results, Case 1-B

Test Results, Case 1-C

Test Results, Case 2-A

Test Results, Case 2-B

Test Results, Case 2-C

Modeling Developing a power model to predict performance for other test cases Power performance a factor of .. Message Length Message Rate Data Rate Component specs Active mode current Idle mode current Operating voltage To be completed before final report

Applications Chip Manufacturer Designers Design our “smart transceiver” capability into next generation products Designers Implement “smart transceiver” solution using small CPLD and memory Offloads CPU from unnecessary processing Ensures data integrity Saves power FOI depends on data rate and message rate

Future Work CPLD Additions Improvements Data receive time-out timer Programmable message length location First byte sent is assumed to be length Improvements CPLD to CPU data transfer Switch from serial to parallel Reduces time to transfer data to CPU Switch from Static SRAM to Dual Port RAM Eliminates the need to transfer data to CPU

Summary PL managed data reception improves power performance in certain cases Best performance Message rate high Data rate low CPU is active nearly continuously Worst performance Message rate low Power is dominated by idle currents