ECE 477 Design Review Team 5  Fall 2006

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Presentation transcript:

ECE 477 Design Review Team 5  Fall 2006 Paste a photo of team members here, annotated with names of team members. From Left: Shawn Ironmonger, Dan Moore, Michael Moninski, James Brown

Outline Project overview Project-specific success criteria Block diagram Component selection rationale Packaging design Schematic and theory of operation PCB layout Software design/development status Project completion timeline Questions / discussion

Project Overview The Smart Poker Table tracks the movement of poker chips records game-play statistics displays game information in real time stores game results on a web page

Project-Specific Success Criteria Ability to output player information to an LCD display. An ability to take user input from a keypad and navigate menus. An ability to track chip movement using RFID. An ability to manage and record statistics of RFID chip movement data. An ability to display statistics over HTTP.

Block Diagram

Component Selection Rationale MC9S12NE64 Large memory Several com ports Built in Ethernet dsPIC30F3012 Multiple com ports Voltage Regulator LP38692MP-3.3,5.0 Level Translators MAX3003 Bi-directional RFID Reader TRRO2OEM Low Frequency

Packaging Design

Schematic/Theory of Operation NE64 Overall View

Schematic/Theory of Operation RJ45 Port

Schematic/Theory of Operation Oscillator Circuit

Schematic/Theory of Operation Reset Circuit

Schematic/Theory of Operation Power Connections

Schematic/Theory of Operation Power Regulator Circuit

Schematic/Theory of Operation Com Ports, Relay port, and RS-232 driving circuit

Schematic/Theory of Operation PIC Overall view

Schematic/Theory of Operation Power Regulator circuit for PIC

Schematic/Theory of Operation Keypad circuit

PCB Layout NE64 Top and Bottom

PCB Layout NE64 Top

PCB Layout NE64 Bottom

PCB Layout Under NE64

PCB Layout Under NE64

PCB Layout PIC Top and Bottom

PCB Layout PIC Top

PCB Layout PIC Bottom

Software Design/Development Status MC9S12NE64 Software architecture has been developed Setup Code for Ethernet and SCI v1 has been implemented All other segments must still be implemented All aspects must be tested dsPIC30F3012 SPI for LCD v1 completed

Project Completion Timeline   Week 8 Week 9 Week 10 Week 11 Week 12 Week 13 Week 14 Week 15 PCB Order all small components Send PCB to FAB RFID Components Working SCI0, I2C, SCI1 on NE64 Working Software up and running on PIC TCP/IP working on NE64 NE64 Talking with PICs over I2C Soldering parts to PCB Debug

Questions / Discussion