CSCE 211: Digital Logic Design Chin-Tser Huang huangct@cse.sc.edu University of South Carolina

Chapter 5: Designing Combinational Systems

Iterative System A system implemented with multiple copies of a smaller circuit Consider 4-bit adder as an example 02/22/2017

Delay in Combinational Logic Circuits When the input to a gate changes, the output of that gate will not change instantaneously Instead, there is a small delay ∆ If the output of one gate is used as the input to another gate, the delays will accumulate The output is stable after the longest delay path 02/22/2017

Delay in Combinational Logic Circuits Hazard (or glitch) 02/22/2017

Example of Delay 02/22/2017

Cascading 4-bit Adders Can cascade multiple 4-bit adders if larger adders are needed 02/22/2017

Binary Decoder A binary decoder is a device that, when activated, selects one of several output lines, based on a coded input signal The input is an n-bit binary number, and there are 2n output lines Some decoders also have one or more enable inputs Decoders are often used to select one of many devices 02/22/2017

Active High Decoder 02/22/2017

Active Low Decoder 02/22/2017

Decoder with Enable 02/22/2017

74138 Decoder 02/22/2017

74138 Decoder 02/22/2017

Use 4 3-to-8 Decoders to Select from 32 Devices 02/22/2017

Use Decoder to Enable Another Decoder 02/22/2017

Multiplexers A multiplexer is a switch that passes one of its data inputs through to the output, as a function of a set of select inputs Sets of multiplexers are often used to choose among several multibit input numbers 02/22/2017

Two-way Multiplexer out = w if S = 0; out = x if S = 1 02/22/2017

Four-way Multiplexer 02/22/2017

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Three-variable Function Implemented with Multiplexer 02/22/2017

Gate Arrays Also known as programmable logic device (PLD) or field programmable gate array (FPGA) An efficient way of implementing complicated systems Can implement SOP expressions which are sums of some common product terms 02/22/2017

Structure of a Gate Array 02/22/2017

An Example of Gate Array f = a’b’ + abc g = a’b’c’ + ab + bc h = a’b’ + c 02/22/2017

Three Types of Combinational Logic Arrays Programmable Logic Array (PLA) User specifies all of the connections in both the AND array and the OR array Read-Only Memory (ROM) The AND array is fixed – like a decoder consisting of 2n AND gates for n inputs User specifies the connections in the OR array Programmable Array Logic (PAL) The connections to the OR gates are specified; user determines the AND gate inputs 02/22/2017

Design with Read-Only Memories Only need a list of minterms for each function. For example, W(A, B, C, D) = ∑m(3, 7, 8, 9, 11, 15) X(A, B, C, D) = ∑m(3, 4, 5, 7, 10, 14, 15) Y(A, B, C, D) = ∑m(1, 5, 7, 11, 15) 02/22/2017

Structure of a PAL 02/22/2017