Topic 5: Processor Architecture 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

Reading List Slides: Topic5x Henn & Patt: Chapter 5 Other papers as assigned in class or homework 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

ABET Outcomes Ability to apply knowledge of science (e.g., computer architecture and system organization, and related computer science issues), and engineering (e.g., performance analysis and benchmarking, ISA simulation and verification) Ability to use the techniques, skills and modern engineering tools necessary for engineering practice Knowledge of related topics in computer science discipline 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

Outline An overview Datapath building blocks Implementation of a simple (single-cycle) datapath Why we will go beyond single-cycle implementation ? 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

Overview The basic instruction execution flow Some conventions 32 bit datapath clocking strategy (edge-triggered) We focus on a subset of MIPS Memory-reference instructions: lw, sw ALU ops: add, sub, and, or Branch equal instructions (beq) and the jump instruction (J) 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

An abstract view of the implementation of the MIPS PC Instruction memory Data Register # Registers ALU Address Memory An abstract view of the implementation of the MIPS subset showing the major functional units and the major connections between them. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

Datapath Components Common to all instructions: Instruction memory PC and its update Datapath of R-R type instructions ALU Register set Datapath of memory-reference instructions ALU (for address calculation) Sign extension unit data memory Datapath for a branch inst. (e.g. beq $1, $2, offset) Sign extension + 2bit shifter Reg Adder ALU (zero output) 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

Instruction memory address ALU Sum PC Write a. Instruction memory b. Program counter c. Adder Two state elements are needed to store and access instructions, and an adder is needed to compute the next instruction address. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

A portion of the datapath used for fetching instructions memory Read address PC Add 4 A portion of the datapath used for fetching instructions and incrementing the program counter. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

The two elements needed to implement R-format ALU result ALU operation Registers Read register 1 data 1 register 2 Write register Data data 2 a. Registers b. ALU Register numbers The two elements needed to implement R-format ALU operation are the register file and the ALU 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

The datapath for R-type instruction Registers Read register 1 data 1 register 2 Write register Data data 2 ALU result Zero Instruction The datapath for R-type instruction 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

Data memory Read address data Write Sign extend 16 32 a. Data memory unit b. Sign-extension unit The two units needed to implement loads and stores are the data memory unit and the sign-extension unit, in addition to the register file and ALU 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

The datapath for a load or store that does a register access memory Read address data Write ALU result Zero Registers register 1 data 1 register 2 register data 2 16 32 Sign extend Instruction The datapath for a load or store that does a register access 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

The datapath for a branch uses an ALU for evaluation of the branch Registers Read register 1 data 1 register 2 Write register Data data 2 Adder Sum ALU Zero 16 32 Shift left 2 Sign extend PC + 4 from instruction datapath Branch target To branch control logic Instruction The datapath for a branch uses an ALU for evaluation of the branch condition and a separate adder for computing the branch target as the sum of the incremented PC and the sign-extended, lower 16 bits of the I instruction (the branch displacement) shifted left 2 bits. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

A Simple (one-cycle) Datapath Implementation No resource can be used more than once by an instruction If used more than once ==> duplicate it! Sharing a resource by 2 or more instructions are done through multiplexing. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

Combining the datapaths for the memory instructions and the R-type instructions 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

The instruction fetch portion of the datapath is appended to the datapath that handles memory and ALU instructions. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

The simple datapath for the MIPS architecture combines the elements required by different instruction classes. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

ALU Control ALU ALU operation Zero Result Overflow a b CarryOut The symbol commonly used to represent an ALU. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder. The control lines labeled ALUOperation . Their values and the ALU operation are found in the next figure. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

ALU Control cont’d ALU Control lines Function 000 And 001 Or 010 Add 110 Subtract 111 Set-on-less-than The values of the three ALU Control lines and the corresponding ALU operations. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

This table shows how the ALU control bits are set depending on the ALUOp control bits and the different function codes for the R-type instruction. The opcode, listed in the first column, determines the setting of the ALUOp bits. All the encoding are shown in binary. Notice that when the ALUOp code is 00 or 01, the output fields do not depend on the function code field; in this case, we say that we “don’t care” about the value of the function code, and the function field is shown as XXXXXX. When the ALUOp value is 10, the function code is used to set the ALU control input. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

Instructions using ALU Load/store: address calculation - add Branch eq: subtract add/subtract R-type: and/or set-on-less-than need function code 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

ALU Control Design The truth table for the three ALU control bits as a function of the ALUOp and function code field. Some don’t care entries have been added. For example, the ALUOp does not use the encoding 11, so the truth table can contain entries 1X, and X1 rather than 10 and 01.. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

The ALU control block generates the three ALU control bits, ALUOp ALU control block ALUOp0 ALUOp1 Operation 2 F3 F2 F1 F0 Operation F (5-0) Operation 1 Operation 0 The ALU control block generates the three ALU control bits, based on the function code and ALUOp bits. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

Features of MIPS Instruction Format Field 0 rs rt rd shamt funct Bit positions 31-26 25-21 20-16 15-11 10-6 5-0 a. R-type instruction Field 35 or 43 rs rt address Bit positions 31-26 25-21 20-16 10-6 b. Load or store instruction Field 4 rs rt address Bit positions 31-26 25-21 20-16 15-0 c. branch instruction 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

Features of MIPS Instruction Format cont’d The op field, also called the opcode, is always contained in bits 31-26. We will refer to this field as Op[5-0]. The two registers to be read are always specified by the rs and rt fields, at positions 25-21 and 20-16. This is true for the R-type instructions, branch equal, and for store. The base register for load and store instructions is always in bit positions 25-21 (rs). The 16-bit offset for branch equal, load, and store is always in positions 15-0. The destination register is in one of two places. For a load it is in bit positions 20-16 (rt), while for an R-type instruction it is in bit positions 15-11 (rd). Thus, we will need to add a multiplex or to select which field of the instruction is used to indicate the register number to be written. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt

The datapath with all necessary multiplexors ALU Add result M u x 1 Read address Instructin memory Instruction (31-0) PC 4 register 1 register 2 Write register data data 1 data 2 Sign extend control Data Zero MemRead Instruction(25-21) Instruction(20-16) Instruction(15-0) RegDst PCSrc MeWrite MemtoReg ALUOp 16 32 Shift left 2 RegWrite Instruction(5-0) Instruction(15:11) The datapath with all necessary multiplexors and all control lines identified. 1/14/2019 \course\cpeg323-08F\Topic5-323.ppt