L15 – Specification of State Machines

Copyright 2012 - Joanne DeGroat, ECE, OSU VHDL State Machines State Machine Basics VHDL for sequential elements VHDL for state machines Example – Tail light controller Example – counter Example – gray code counter Ref: text Unit 10, 17, 20 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU State Machine Basics Mealy machine – outputs are a function of current state and current inputs. Moore machine – outputs are a function of the current state only. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU State machine design To implement the state machine have option to use Traditional methodology – state graph, state table, state assignment, K-maps, implementation HDL methodology HDL description directly from word description State graph and then the HDL description 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

In HDLs need state elements HDL code for the F/Fs A simple rising edge D Flip Flop ARCHITECTURE xxx OF yyy IS BEGIN PROCESS WAIT UNTIL clk=‘1’ AND clk’event; state <= next_state; END PROCESS; Semantics : Process runs at time 0 and then holds for clock to have an event (change value) and the new value is a ‘1’. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU Another Form This is an alternative to the previous HDL ARCHITECTURE xxx OF yyy IS BEGIN PROCESS (clk) IF (clk=‘1’ AND clk’event) THEN state <= next_state; END IF; END PROCESS; Semantics – Process runs once at time 0 and then holds until signal clk has an event. It then executes the IF statement. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU D F/F with reset ENTITY dff IS PORT (clk,reset,din : IN bit; qout : OUT bit); END dff; ARCHITECTURE one of dff IS -- Entity had sig clk,reset,din: IN and qout:OUT -- td_reset and td_in are constants. BEGIN PROCESS (clk) IF (clk=‘0’ AND clk’event) THEN IF (reset =‘1’) THEN qout <=‘0’ AFTER td_reset; ELSE qout <= din AFTER td_in; END IF; END PROCESS; END one; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU More complete D F/F PROCESS (clk,preset,clear,next_state) BEGIN -- active low preset and clear IF (preset = ‘0’) THEN state <= pr_state; --preset state ELSIF (clear = ‘0’) THEN state <= clr_state; --clear state ELSIF (clk = ‘1’ AND clk’event) THEN --rising edge state <= next_state; END IF; END PROCESS; Semantics – runs once at startup. Then whenever any of the signals in the sensitivity list change value. Asynchronous preset has priority over clear and a clock edge. clear has priority over a clock edge. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

VHDL for finite state machines Use a process to describe the next state logic, often in a case statement used for determination of the next state. Will see this in the example. Use a process to represent the latching/loading of the calculated next_state such that it becomes the current_state. This is the only process that generates sequential elements (F/Fs). The other processes represent combinational logic. Use a third process to represent the generation of the outputs from the current state and possibly the inputs. This process will have as its inputs, the current state and, depending on the type of state machine, the state machine inputs. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU Notes on VHDL style The style applies to any HDL – VHDL, Verilog, System C Documents well Easily maintainable – excellent during development as changes are easily made Style maps to physical logic – using this style can predict the number of state elements (~) that should be produced by synthesis All three styles on the last slide simulate equally well, but this style also synthesizes well. Works in XILINX and Altera tools. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU Example The T-Bird tail light problem The turn signal indicator had a light sequence on each lamp. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

State machine description State Diagram and Transition Table Output is associated with state – a Moore machine 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Goal is a HDL description Often you still start with a state diagram and state table Where to start with the code? As with all HDL – start with the interface WHAT ARE THE INPUTS AND OUTPUTS? 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

ENTITY for the controller Inputs are a signal for Right turn signal Left turn signal Hazard Clock Outputs are signals for the taillights lc, lb, la rc, rb, ra HDL code for the entity ENTITY t_bird IS PORT(rts,lts,haz : IN bit; clk : IN bit; lc,lb,la : OUT bit; ra,rb,rc : OUT bit); END t_bird; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

For the tail light controller Inputs are signals for Right Turn Signal Left Turn Signal Hazard Clock Outputs are the signals for the lights la,lb,la ra,rb,rc 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU The ARCHITECTURE Will use 3 processes In declarative region of ARCHITECTURE will declare the state_type for the states. ARCHITECTURE state_machine OF t_bird IS TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3); SIGNAL state,next_state : state_type; BEGIN 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

1st Process – sequential elements Use a process to specify the sequential elements Here need only simple D F/Fs -- Process to specify F/Fs PROCESS BEGIN WAIT UNTIL clk=‘1’ AND clk’event; state <= next_state; END PROCESS; This is the only part of the description that should result in state elements from synthesis. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

2nd Process – next state generation What is the next state given the current state and the value present on the inputs? This process can be of considerable size. Work well using a case statement. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU Next State Process Code continued A separate action for each state that based on the inputs directs the value assigned to next_state. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

3rd Process – Output signals A separate process is used to generate the final outputs. Works great for Moore type implementations. Outputs are directly assigned to. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Complete VHDL code (no output) ENTITY t_bird IS PORT(rts,lts,haz, : IN bit; clk : IN bit; lc,lb,la : OUT bit; ra,rb,rc : OUT bit); END t_bird; ARCHITECTURE state_mach OF t_bird IS TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3); SIGNAL state,next_state : state_type; BEGIN -- Process to specify F/Fs PROCESS WAIT UNTIL clk=‘1’ AND clk’event; state <= next_state; END PROCESS; -- next state logic PROCESS BEGIN CASE state IS WHEN idle => IF(haz=‘1’ OR (lts=‘1’ AND rts =‘1’) THEN next_state <= lr3; ELSIF (haz=‘0’ AND (lts=‘0’ AND rts=‘1’) THEN next_state<=r1; ELSIF (haz=‘0’ AND (lts=‘’1’ AND rts=‘0’) THEN next_state<=l1; ELSE next_state <= idle; END IF: WHEN l1 => IF (haz=‘1’) THEN next_state <= lr3; ELSE next_state <= l2; END IF; WHEN l2 => IF (haz=‘1’) THEN next_state <= lr3; ELSE next_state <= l3; WHEN l3 => next_state <= idle; WHEN r1 => IF (haz=‘1’) THEN next_state <= lr3; ELSE next_state <= r2; WHEN r2 => IF (haz=‘1’) THEN next_state <= lr3; ELSE next_state <= r3; WHEN r3 => next_state <= idle; WHEN lr3 => next_state <= idle; END CASE; END PROCESS; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Having HDL description Simulate it in a test suite to verify the design meets specifications. This is the HDL topic of verification. For this course will construct simple testbenches to do simple check. HDL code can also be synthesized. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU Results of synthesis From a Mentor graphics tool (several years back) 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU From FPGA tools When done in Quartis – ALTERA FPGA tool Use the state machine VHDL code for synthesis 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU FPGA results From the report Combination LUTs – 15 Dedicated logic registers – 8 (did a one hot encoding) Total pins 10 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU The schematic Big block for state elements 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU The implementation The one hot state machine state diagram 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU Lecture summary VHDL for state machines T_bird tail light controller example VHDL Synthesis results 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU