Design Language 최기영 (서울대학교, 전기컴퓨터공학부) Copyrightⓒ2003

과목 개요(Learning Map) SoC Design Methodoloy Design Flow Classes Lab. Ÿ Soc Design Flow Introduction Ÿ Design Reuse & SoC Platform Specification Ÿ System Specification System Spec. Lab. Ÿ HW/SW Interface Design Ÿ Power Estimation & Management Design Design Language Lab. Ÿ DSM Design & Signal Integrity Ÿ Design Language Ÿ Synthesis Synthesis Ÿ Architecture Mapping Ÿ Verification Verification Ÿ HW/SW Co-simulation Co-simulation Lab. Ÿ Prototyping & Emulation Ÿ SoC Testing Test SoC Test Lab. Ÿ Design for Testability Copyrightⓒ2003

Outline Introduction Fundamentals of SystemC Levels of Abstraction Conventional HDL-based design System design language SystemC Fundamentals of SystemC Model of time Clocks Modules Interfaces, ports, and channels Processes Data types Levels of Abstraction Design flow Why TLM? References Copyrightⓒ2003

Introduction Conventional HDL-based design Problems Disconnect between system model and HDL model Manual Conversion from C to HDL is time consuming and error prone Test created for C model can’t be run against HDL model Specification Modeling In C/C++ Modeling In HDL Verification In C/C++ Verification In HDL manual conversion Synthesis Need a uniform system modeling language Copyrightⓒ2003

System design language Requirements Modeling at various levels of abstraction Support SW as well as HW Executable specification for easy simulation and evaluation Fast simulation for efficient design space exploration Accurate modeling Separation of computation from communication for design reuse Support good design tools/environment Examples C/C++-based: SystemC, SpecC HDL-based: SystemVerilog Copyrightⓒ2003

SystemVerilog Extension to Verilog Key enhancements A unified assertion language for both simulation and formal verification Object oriented C++ like classes Interfaces to encapsulate communication and protocol checking C like data types such as int Enumerated types Type casting Structures and unions Strings and dynamic arrays Pass by reference to tasks, functions, and modules Semaphore and mailbox inter-process communication and synchronization Direct Programming Interface (DPI) for direct call to C functions and Verilog functions Copyrightⓒ2003

SystemVerilog history Verilog (Gateway) 1989 Cadence acquired Gateway and opened Verilog 1995 IEEE standardize Verilog (IEEE Std. 1364), Verilog 95 1997 SUPERLOG (Co-Design) 2001 Verilog 01 2002 SystemVerilog V3.0 (Accellera) 2003 SystemVerilog V3.1 Copyrightⓒ2003

SpecC Extension to ANSI-C Constructs are added to support History Behavioral and structural hierarchy Concurrency Timing Communication (behavior, channel, interface) Synchronization (event, wait, notify) State transition for FSM Exception handling (abortion, interrupt) Hardware data types (bit-vector) History First version was developed in 1997 at UC Irvine. SpecC Open Technology Consortium (STOC) was founded in 1999. SpecC v2.0 approved by STOC in 2002 Copyrightⓒ2003

SystemC C++ class library to create a cycle-accurate model of software algorithms, hardware architecture, and interfaces of SoC Constructs added to standard C++ Notion of time Concurrency Reactive behavior Hardware data types Advantages Familiar to the engineering community Easy to write and debug Concurrent design of software and hardware Fast simulation Can use C/C++ programming environments Copyrightⓒ2003

SystemC V0.9 by OSCI (Open SystemC Initiative) SystemC history Scenic UC Irvine Synopsys Frontier Design IMEC Mid of 1990s SystemC V0.9 by OSCI (Open SystemC Initiative) 1999 SystemC V1.0 2000 SystemC V2.0 2001 Copyrightⓒ2003

OSCI working groups Language Working Group Verification Working Group Core language development and standardizing Verification Working Group Generating intelligent testbenches Transaction-based verification methods Dataflow Working Group Library extension for supporting dataflow modeling IP Integration Working Group IP block modeling and reuse methodology in SystemC Analog-Mixed-Signal Working Group Transaction API Working Group Copyrightⓒ2003

Methodology-Specific Language architecture Standard Channels for Various MOC's Kahn Process Networks Static Dataflow, etc. Methodology-Specific Channels Master/Slave Library, etc. Elementary Channels Signal, Timer, Mutex, Semaphore, Fifo, etc. Core Language Modules Ports Processes Interfaces Channels Events Data Types Logic Type (01XZ) Logic Vectors Bits and Bit Vectors Arbitrary Precision Integers Fixed Point Integers Integers C++ Language Standard Copyrightⓒ2003

Design environment Copyrightⓒ2003

Fundamentals of SystemC Model of Time Type of time is 64 bit unsigned integer. Time unit SC_FS, SC_PS, SC_NS, SC_US, SC_MS, SC_SEC Time object (sc_time class) Represents time value Ex) sc_time t1(15, SC_PS); // t1 represents 15ps Time resolution The smallest amount of time that can be represented by all sc_time objects. Any time smaller than the time resolution will be rounded off, using round-to-nearest. Default value of time resolution is 1ps. Set by using sc_set_time_resolution() Ex) sc_set_time_resolution(10, SC_PS); Copyrightⓒ2003

Clocks Clock objects generate timing signals used to synchronize events in the simulation. Create a clock object sc_clock clock_name(“clock_name”, period, duty_cycle, time_to_first_edge, first_edge_positive); Ex) sc_clock clk1(“clk1”, 10, 0.5, 0, true); Period 10 time units, a duty cycle of 50%, the first edge will occur at 0 time units, and the first value to true Member functions name(): returns clock name period(): returns clock period in ‘sc_time’ class duty_cycle(): returns clock duty cycle signal(): returns current Boolean value of the clock Copyrightⓒ2003

Modules Basic building block to partition a design Properties Break complex systems into smaller more manageable pieces Hide internal data representation and algorithms from other modules Declaration SC_MODULE(module_name){ struct module_name : sc_module { Module contains some elements Ports Local signals Local data Other modules Processes Constructors module process process module module Copyrightⓒ2003

Array ports and signals the external interface that pass information to and from a module Signals connections between module ports allowing modules to communicate Ports are always bound to a signal except for one case where a port is bound directly to another port. Array ports and signals Multiple ports or signals can be defined. Syntax for ports sc_in< data_type> port_name[n]; Create ports port_name[0] to port_name[n-1] of type data_type Syntax for signals sc_signal< data_type> signal_name[n]; Create signals signal_name[0] to signal_name[n-1] of type data_type Copyrightⓒ2003

Connecting signals to ports Named mapping Each signal connects to the port by its name. Positional mapping Each signal connects to the port in turns. SC_MODULE(Add3) { sc_in<int> in1; sc_in<int> in2; sc_in<int> in3; sc_in<int> sum; sc_signal<int> temp; Adder* adder1; Adder* adder2; SC_CTOR(Add3) { adder1 = new Adder(“adder1”); (*adder1) (in1, in2, temp); adder2 = new Adder(“adder2”); adder2->a(temp); adder2->c(sum); adder2->b(in3); } }; Positional mapping Named mapping Copyrightⓒ2003

Resolved logic vectors Multiple drivers are driving a signal Resolution table x=0 A y=1 g=X B z=Z C Syntax sc_in_rv<n> x; // input resolved logic vector n bits wide sc_out_rv<n> y; sc_inout_rv<n> z; X Z 1 Copyrightⓒ2003

Reading and writing ports and signals Use read() and write() methods sc_in<int> in_data; sc_out<int> out_data; int a; a = in_data.read(); out_data.write(10); Use assignment operator a = in_data; out_data = 10; Copyrightⓒ2003

Constructors Identifies processes in the module Assigns sensitivity list to each process Initializes the variables used in the module SC_CTOR(module_name){…}; Macro that declares constructor of class Assign only module name SC_HAS_PROCESS(module_name); Can use additional parameters SC_MODULE(Adder){ SC_CTOR(Adder){ // body } SC_MODULE(Adder){ SC_HAS_PROCESS(Adder); Adder(sc_module_name name, int other_param) : sc_module(name) { // body } Copyrightⓒ2003

Interfaces, Ports, and Channels Interfaces, ports and channels are defined for process synchronization and communication refinement. An interface declares a set of methods, but does not implement the details. A channel implements one or more interfaces. A port enables a module to access a channel’s interface method. Copyrightⓒ2003

Interfaces Interfaces declare channel access methods. Define only name, parameter and return value A port that is connected to a channel through an interface sees only those channel methods that are defined by the interface. All interfaces are derived from base class sc_interface. Copyrightⓒ2003

Ports An object through which a module can access a channel’s interface Three basic port types sc_in<T> : transfers data into a module sc_out<T>: transfers data out from a module sc_inout<T>: transfers data both into and out of a module depending on module operation Specialized ports Can be created by refining port base class sc_port or the predefined port types Copyrightⓒ2003

Channels Channels implement one or more interfaces and serves as a container for communication functionality. A channel may be connected to more than two modules. Primitive channels Do not exhibit any visible structure Do not contain processes Cannot access other primitive channels Ex) sc_signal<T>, sc_fifo<T>, sc_mutex, sc_mq Hierarchical channels Can have structures, contain other modules and processes, and access other channels Copyrightⓒ2003

Processes The basic unit of execution Model the parallel activities of a system A member function with no argument and no return value Registered as a process within module constructor (SC_CTOR) Processes run concurrently, but code inside a process is sequential. Processes are not hierarchical, so no process will call another process directly, but can call methods and functions that are not process. Processes have sensitivity lists. Copyrightⓒ2003

Process Types Method process - SC_METHOD() Suitable for implementing combinational logic Fastest type Thread process - SC_THREAD() Suitable for implementing behavioral testbench Require context switch Clocked thread process - SC_CTHREAD() Suitable for implementing synchronous logic or FSM Only triggered on one edge of a clock Copyrightⓒ2003

Method Process - SC_METHOD Process executes when value changes occur on signals in the sensitivity list. The method executes and returns control back to the simulation kernel. Cannot contain wait() calls and infinite loops Once it returns the control to the kernel, the implicit execution state is lost. Copyrightⓒ2003

Thread Process – SC_THREAD Can be suspended and reactivated Suspended when wait() functions is called Reactivated when one of the signals in sensitivity lists is changed Slower than SC_METHOD processes Dynamic sensitivity For event wait(e1 & e2); // wait on e1 and e2 For time Wait(100, SC_NS); // wait for 100ns For both event and time Wait(100, SC_NS, e); // wait on event e, timeout after 100ns Copyrightⓒ2003

Clocked Thread Process – SC_CTHREAD Special case of a Thread Process Triggered on one edge of a clock SC_CTHREAD does not have a separate sensitivity list Suspended Using wait() method Until a condition is satisfied using wait_until() Ex) wait_until(sensor.delayed() == true); Reactivated when the clock edge occurs Copyrightⓒ2003

Sensitivity A list of signals that cause the process to be invoked, whenever the value of a signal in this list changes Syntax Sensitive << signal_name << signal_name << …; Example SC_MODULE ( test_module ) { sc_in<int> inA, inB; sc_in<bool> clock; void do_thread(); SC_CTOR( test_module ) { SC_THREAD( do_thread); sensitive << inA<< inB; sensitive_pos << clock; } }; Copyrightⓒ2003

Watching Initialize the behavior of infinite loop or jump out of the loop when a condition occurs When condition occurs, control is transferred from the current execution point to the beginning of the process. Example void gen_data() { if(reset == true) { data = 0; } while (true) { data = data + 1; wait(); data = data + 2; data = data + 4; SC_MODULE(data_gen){ sc_in_clk clk; sc_inout<int> data; sc_in<bool> reset; void gen_data(); SC_CTOR(data_gen){ SC_CTHREAD(gen_data, clk.pos()); watching(reset.delayed() == true); } }; Copyrightⓒ2003

Data Types C++ built in types SystemC types User defined types int, char, short, long, float, double SystemC types Boolean types sc_bit Logic types sc_logic Integer types sc_int<n>, sc_uint<n>, sc_bigint<n>, sc_biguint<n> Boolean/logic vector types sc_bv<n>, sc_lv<n> Fixed point types sc_fixed, sc_ufixed, sc_fix, sc_ufix User defined types Copyrightⓒ2003

Boolean Types & Logic Types Boolean type - sc_bit Two valued data type representing a single bit – ‘0’ or ‘1’ Operators Bitwise: &(and), |(or), ^(xor), ~(not) Assignment: =, &=, |=, ^= Equality: ==, != Logical type - sc_logic 4 values - ‘0’, ‘1’, ‘X’, ‘Z’ Bitwise: &, |, ^, ~ Copyrightⓒ2003

Integer Types Type sc_int<n> and sc_uint<n> Fixed precision signed and unsigned integer Two’s complement representation for signed integer Based on 64 bit integer Operators Bitwise: &, |, ^, ~, >>, << Arithmetic: +, -, *, /, % Assignment: =, +=, -=, *=, /=, %=, &=, |=, ^= Equality: ==, != Relational: <. <=. >. >= Auto increment (decrement): ++, -- Bit select: [x] Part select: range() Concatenation: (,) Copyrightⓒ2003

Type sc_bigint and sc_biguint Arbitrary precision signed and unsigned integer They work with any operand sizes, but should only be used on operands larger than 64 bits. They execute more slowly than their fixed precision counterparts Operators Bitwise: &, |, ^, ~, >>, << Arithmetic: +, -, *, /, % Assignment: =, +=, -=, *=, /=, %=, &=, |=, ^= Equality: ==, != Relational: <. <=. >. >= Auto increment (decrement): ++, -- Bit select: [x] Part select: range() Concatenation: (,) Copyrightⓒ2003

Boolean/Logic Vector Types Type sc_bv and sc_lv Arbitrary length bit/logic vector New operators: bit reduction Take the entire set of bits of the operand and generate a single bit result Operators Bitwise: &, |, ^, ~, >>, << Assignment: =, &=, |=, ^= Equality: ==, != Bit select: [x] Part select: range() Concatenation: (,) Reduction: and_reduction(), or_reduction(), xor_reduction() Copyrightⓒ2003

xxxx00. xxx.xx Static Fixed Point Types Use static arguments to specify the functionality of the type Static arguments must be known at compile time sc_fixed< wl, iwl, q_mode, o_mode, n_bits> name; sc_ufixed< wl, iwl, q_mode, o_mode, n_bits> name; wl: total word length iwl: integer word length q_mode: quantization mode o_mode: overflow mode n_bits: number of saturated bits Example xxxx00. wl = 4 iwl = 6 xxx.xx wl = 5 iwl = 3 Copyrightⓒ2003

Dynamic Fixed Point Types Use dynamic arguments to specify the functionality of the type Dynamic arguments must be set before the object is instantiated. sc_fix<wl, iwl, q_mode, o_mode, n_bits> name; sc_ufix<wl, iwl, q_mode, o_mode, n_bits> name; Copyrightⓒ2003

The resulting operand is cast to fit the fixed point data type object Quantization Modes The resulting operand is cast to fit the fixed point data type object Default: SC_TRN Mode Name Rounding to plus infinity SC_RND Rounding to zero SC_RND_ZERO Rounding to minus infinity SC_RND_MIN_INF Rounding to infinity SC_RND_INF Convergent rounding SC_RND_CONV Truncation SC_TRN Truncation to zero SC_TRN_ZERO SC_TRN Copyrightⓒ2003

Overflow Modes Default: SC_WRAP, n_bits=0 Mode Name Saturation SC_SAT Saturation to zero SC_SAT_ZERO Symmetrical saturation SC_SAT_SYM Wrap-around SC_WRAP Sign magnitude wrap-around SC_WRAP_SM SC_WRAP, n_bits=0 Copyrightⓒ2003

(Register Transfer Level) Levels of Abstraction Design Flow UTF (Untimed Functional) Refine TF (Timed Functional) Partition Software Hardware Abstract RTOS BCA (Bus Cycle Accurate) Refine Synthesis RTL (Register Transfer Level) Target Code Synthesis Netlist Copyrightⓒ2003

Untimed Functional (UTF) A network of HW/SW neutral modules executing in zero time and communicating thru abstract channels Timed Functional (TF) A network of modules executing in some defined times and communicating thru abstract channels The execution times are assigned using wait(delay). Bus Cycle Accurate (BCA) A network of modules executing in some defined times and communicating thru abstract buses Not pin level accurate --> Transaction Level Model (TLM) Cycle Accurate (CA) Register Transfer Level (RTL) Pin level accurate Models behavior at the system clock level Copyrightⓒ2003

Transaction Level Modeling TLM is easier --> Start software development early To speed up simulation of system design for (i=0; i<NumberMDU; i++) { ... ChenDct(input, output); } Processor (ARM9) BUS (AMBA AHB) Memory HW (DCT) Decoder void ChenDct(int *x, int *y) { ... for(i=0;i<8;i++) { } for(i=0,aptr=y;i<64;i++,aptr++) { *aptr = (((*aptr<0) ? (*aptr-4) : (*aptr+4))/8); Copyrightⓒ2003

Implement DCT in HW Processor Decoder (ARM9) BUS (AMBA AHB) Memory HW void ChenDct(int *x, int *y) { ... for(i=0;i<8;i++) { } for(i=0,aptr=y;i<64;i++,aptr++) { *aptr = (((*aptr<0) ? (*aptr-4) : (*aptr+4))/8); Processor (ARM9) Decoder void ChenDct(int *x, int *y) { ... for(i=0; i<64; i++) *(DCT_DATA_P + i) = x[i]; DCT_START_P = START_COMMAND; while(*DCT_DONE_P == 0); for(i=0;i<64;i++) y[i]=*(DCT_DATA_P + i); } BUS (AMBA AHB) Memory DONE DATA START HW (DCT) Copyrightⓒ2003

RTL modeling ISS Processor (ARM9) Decoder BUS Interface BUS (AMBA AHB) HDL Simulation at the RTL CLK SEL WRITE ADDR[31:0] RDATA[31:0] WDATA[31:0] ... Memory HW (DCT) Copyrightⓒ2003

TL modeling in SystemC ISS Processor (ARM9) Decoder BUS Interface BUS (AMBA AHB) SystemC Simulation at the TL class DCT : public sc_module, public ahb_slave_if { ... void read(ahb_addr_t, int); void write(ahb_addr_t, int); void set_data(int, ahb_data_t); }; Memory HW (DCT) Copyrightⓒ2003

References S. Sutherland, S. Davidmann, and P. Flake, SystemVerilog for Design, Kluwer Academic Publishers, 2004. SpecC Language Reference Manual Version 2.0, Available from the SpecC Technology Open Consortium (STOC) at http://www.specc.gr.jp/eng/tech/SpecC_LRM_20.pdf. SystemC Version 2.0.1 User’s Guide, 2002, Available from the Open SystemC Initiative (OSCI) at http://www.systemc.org/projects/sitedocs/document/v201_Users_guide/en/1. Functional Specification for SystemC 2.0.1, 2002, Available from the Open SystemC Initiative (OSCI) at http://www.systemc.org/projects/sitedocs/document/v201_Func_Spec/en/1. T. Grotker, S. Liao, G. Martin, and S. Swan, System Design with SystemC, Kluwer Academic Publishers, 2002. J. Gerlach and W. Rosenstiel, "System level design using the SystemC modeling platform," Proc. Workshop on System Design Automation, March 2000. Copyrightⓒ2003