UNIT 19 PWM 로봇 SW 교육원 조용수

학습 목표 PWM PWM Register

PWM Pulse Width Modulation 진폭이 일정한 상태에서 펄스 폭을 증/감 하여 신호를 변화시키는 방법 디지털 출력으로 아날로그 회로를 제어할 수 있음. Duty Cycle : High Level 과 Low Level 간의 비율

N051 PWM Four PWM Generators, each generator supports One 8-bit prescaler One clock divider ( 1, ½, ¼, 1/8, 1/16) Two PWM-timers for two outputs, each timer includes A 16-bit PWM down-counter A 16-bit PWM reload value register (CNR) A 16-bit PWM compare register (CMR) One dead-zone generator Two PWM outputs. 8 PWM channels or 4 PWM paired channels. 16 bits resolution. Support edge and center aligned modes Single-shot or Continuous mode PWM.

PWM/Capture Clock Source

PWM Edge Align Mode Duty ratio = (CMR+1) / (CNR+1) Duty = (CMR+1) x (clock period) Period = (CNR+1) x (clock period)

PWM Double Buffering Illustration S/W write new period (CNR) And new duty (CMR) First cycle Second cycle New period (CNR) New duty (CMR)

Operation of Dead Zone Generator Why need the dead zone control? To avoid a paired-PWM outputs overlapping on duty-on duration. For example, in Motor Driver application, it needs to avoid the upper and lower power switch turn on simultaneously. Insert a delay time (dead zone) before duty on at each channel of paired-PWM. 8-bit dead-zone timer from PWM clock.

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