Advanced FPGA Based System Design

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Presentation transcript:

Advanced FPGA Based System Design Lecture-11 & 12 VHDL Finite State Machines By: Dr Imtiaz Hussain imtiaz.hussain@faculty.muet.edu.pk

Contents Finite State Machines Signals & Variables Design Style#1

Introduction Several approaches can be conceived to design a FSM. We will discuss in detail one style that is well structured and easily applicable.

Design Style#1 In this style, the design of the lower section of the state machine is completely separated from that of the upper section.

Design Style#1 It contains user-defined enumerated data type (here called state), which lists all possible states of the machine.

Design Style#1 Design of Lower (Sequential) section The flip-flops are in the lower section, so clock and reset are connected to it. The other lower section’s input is nx_state (next state), while pr_state (present state) is its only output. Being the circuit of the lower (sequential) section, a PROCESS is required, in which any of the sequential statements (IF, WAIT, CASE, or LOOP, can be employed.

Design Style#1 Design of Lower (Sequential) section A typical design template for the lower section is the following:

Design Style#1 Design of Upper (Combinational) section The upper section is fully combinational, so its code does not need to be sequential; concurrent code can be used as well. In the design template shown in next slide, sequential code is employed, with the CASE statement playing the central role.

Example-1 A BCD counter is an example of Moore Machine

Example-1

Example-1

Example-1

Example-1

Example#2 The system has two states (state A and state B). State must change from one to the other every time d = ‘1’ is received. The desired output is x = a when the machine is in state A, or x =b when in state B. The initial (reset) state is state A.

Example#2

Example#2

Example#2