Analog Front-end electronics for the outer layers of the SuperB SVT: design and expected performances Luca Bombelli1,2 on behalf of the SVT-SuperB Group. 1 Politecnico di Milano, Dipartimento di Elettronica e Informazione, Milano, Italy 2 INFN, Sezione di Milano, Milano, Italy Readout architecture of the SVT strip readout chips for the outer layer. Noise Estimation Strip side Layer Peaking time (ns) Total ENC nominal case (el) x5 leakage current (el) Phi 4 375 1331 500 1291 Z 1294 1222 1164 5 1282 1289 750 1180 1217 1000 1145 1209 1252 1259 1106 1135 1035 1088 Detector Model including: Strip ganging Fanout parasitic Radiation damage (leakage increase) Electronic contribution

TS and Time walk error rms (ns) Analog Front-end electronics for the outer layers of the SuperB SVT: design and expected performances Efficiency simulation using TOT Time domain simulation with hits energy distribution according to the expected background spectrum. Efficiency for L4 and L5: > 97% (nominal background rate, long peak-time) > 92% (x5 background rate, short peak-time) Expected Timing Resolution Peaking time (ns) TOT bit TOT clock (Mhz) TS and Time walk error rms (ns) Jitter for 0.3 MIP (ns) Time resolution (ns) 375 4 11.3 33 35 48 6 47.5 15 38 500 8.5 41 43 59 35.7 17 46 750 5.66 56 60 82 23.8 21 64 1000 4.25 72 78 106 17.8 25 250ns Residual error of time-stamp and time-walk correction