The Inverter EE4271 VLSI Design Professor Shiyan Hu Office: EERC 518

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Presentation transcript:

The Inverter EE4271 VLSI Design Professor Shiyan Hu Office: EERC 518 shiyan@mtu.edu The Inverter Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

Circuit Symbols

The CMOS Inverter: A First Glance out C L DD S D Vin=Vdd,Vout=0 Vin=0,Vout=Vdd

CMOS Inverter - First-Order DC Analysis DD in out R n p

CMOS Inverter: Transient Response DD DD Delay=0.69RC R p V out V out C L C L R n V V V in in DD (a) Low-to-high (b) High-to-low

NMOS In Inverter S D V C in out L DD For NMOS Vin=0, Vgsn=0<Vtn, Vdsn=Vout=Vdd, NMOS is in cut-off region, X1. PMOS is on. Vout=Vdd. Vin=Vdd, instantaneously, Vgsn=Vdd>Vtn,Vdsn=Vout=Vdd, Vgsn-Vtn=Vdd-Vtn<Vdd, NMOS is in saturation region, X2 Instantaneously, Vgsp=0>Vtp. PMOS cut-off NMOS is on so Vdsn->0. The operating point follows the arrow to the origin. Vout=0 at X3. NMOS In Inverter V in out C L DD S D

The CMOS Inverter Assume that Idsp=-Idsn when both transistors are on and Vtn=|Vtp| V in out C L DD S D

The CMOS Inverter – 2 (Region A) 0<Vin<Vtn V in out C L DD |Vgsp|=|Vin-Vdd|>|Vtp|, |Vdsp|=|Vd-Vdd|~0<|Vgsp-Vtp| PMOS linear region S D Vd is close to Vdd D S Vgsn=Vin<Vtn, NMOS cut-off

The CMOS Inverter – 3 (Region B) Vtn<Vin<Vdd/2 V in out C L DD |Vgsp|=|Vin-Vdd|>Vdd/2>|Vtp|, |Vdsp|~0<|Vgsp-Vtp| PMOS linear region S D D S Vgsn=Vin>Vtn, Vdsn=Vout=Vdd>Vgsn-Vtn NMOS saturation region

The CMOS Inverter - 4

The CMOS Inverter – 5 (Region C) Vin=Vdd/2 V in out C L DD |Vgsp|=|Vin-Vdd|>|Vtp|, |Vdsp|>|Vgsp-Vtp|, saturation S D D S Vgsn>Vtn, Vdsn>Vgsn-Vtn, saturation

The CMOS Inverter - 6 Usually, Usually we set for equal rising and falling propagation delay (same R for both devices) Since , we have

The CMOS Inverter 7 Vin=Vout=Vdd/2 The above analysis is actually correct for Vin=vdd/2 and all Vout such that both devices are in saturation regions For NMOS, Vout>Vin-Vtn For PMOS, Vgsp-Vtp>Vdsp ->Vout<Vin-Vtp Vin-Vtn<Vout<Vin-Vtp, so for Vin=Vdd/2, Vout can vary around Vdd/2

The CMOS Inverter – 9 (Region D) Vdd/2<Vin<Vdd-|Vtp| V in out C L DD |Vgsp|=|Vin-Vdd|>|Vtp|, |Vdsp|=|Vd-Vdd|>|Vgsp-Vtp|, PMOS saturation region S D D S Vgsn=Vin>Vtn, Vdsn=Vout<Vgsn-Vtn NMOS linear region

The CMOS Inverter - 10

The CMOS Inverter – 11 (Region E) Vin>Vdd-|Vtp| V in out C L DD |Vgsp|=|Vin-Vdd|<|Vtp|, PMOS cut-off S D D S Vgsn=Vin>Vtn, Vdsn<Vgsn-Vtn NMOS linear

The CMOS Inverter -12

The CMOS Inverter

Circuit Under Design

Its Layout View