嵌入式微控制器编程 Embedded Microcontroller Programming 先学习一个完整的汇编语言程序是怎样构成的： 一个源文件的典型构成；汇编语句的一般格式；汇编语句中的各种成分；汇编语言分析； 继而学习如何由多个汇编语言文件完成一个项目； 为一个应用编写多个汇编语言文件；子函数的调用；变量的共享；参数传递等等； 后面的课程要学习如何用C和汇编混合完成一个应用项目； 然后就是如何充分利用ARM的存储管理系统和中断处理机制； 再后就是利用上述技术来为具体的系统开发系统程序和应用程序了。 艾云峰 aiyunfeng@gmail.com

内容大纲 S3C2440A Clock & Power Management S3C2440A Watch Dog Timer 2019/1/16 SST@BJUT

2019/1/16 SST@BJUT

EMDK 3000外接晶振 2019/1/16 SST@BJUT

概述(1) The Clock & Power management block consists of three parts: Clock control unit USB control Power control Clock control logic generate the required clock signals including FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals，UCLL for USB two Phase Locked Loops (PLLs) one for FCLK, HCLK, and PCLK, the other dedicated for USB block (48Mhz) make slow clocks without PLL connect/disconnect the clock to each peripheral block by software 2019/1/16 SST@BJUT

概述(2) power control logic has various power management schemes to keep optimal power consumption for a given task can activate four modes: NORMAL mode, SLOW mode, IDLE mode, and SLEEP mode 2019/1/16 SST@BJUT

时钟体系结构图 2019/1/16 SST@BJUT

CLOCK SOURCE SELECTION The OM[3:2] status is latched internally by referring the OM3 and OM2 pins at the rising edge of nRESET EMDK 300中OM2 OM3接地 所以时钟源为外接晶振 MPLLin = 16.9344MHZ 2019/1/16 SST@BJUT

MPLL The UPLL within the clock generator is similar to the MPLL in every aspect. 2019/1/16 SST@BJUT

Mpll(FCLK)选择表 2019/1/16 SST@BJUT

CLOCK CONTROL LOGIC determines the clock source to be used, i.e., the PLL clock (Mpll) or the direct external clock (XTIpll or EXTCLK). When to a new PLL is configured frequency value, the clock control logic disables the FCLK until the PLL output is stabilized using the PLL locking time. The clock control logic is also activated at power-on reset and wakeup from power-down mode. 2019/1/16 SST@BJUT

Selection of dividing ratio(1) FCLK is used by ARM920T. HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB host block PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface,ADC, UART, GPIO, RTC and SPI. 2019/1/16 SST@BJUT

Selection of dividing ratio(2) The S3C2440A supports selection of Dividing Ratio between FCLK, HLCK and PCLK. This ratio is determined by HDIVN and PDIVN of CLKDIVN control register. 2019/1/16 SST@BJUT

CLOCK & Power Managemetn Register 2019/1/16 SST@BJUT

LOCK TIME COUNT REGISTER (LOCKTIME) 2019/1/16 SST@BJUT

PLL CONTROL REGISTER (MPLLCON & UPLLCON) 2019/1/16 SST@BJUT

CLOCK CONTROL REGISTER (CLKCON) 2019/1/16 SST@BJUT

CLOCK SLOW CONTROL (CLKSLOW) REGISTER 2019/1/16 SST@BJUT

CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER 2019/1/16 SST@BJUT

CAMERA CLOCK DIVIDER (CAMDIVN) REGISTER 2019/1/16 SST@BJUT

POWER MANAGEMENT Overview(1) The Power Management block controls the system clocks by software for the reduction of power consumption in the S3C2440A These schemes are related to PLL, clock control logics (FCLK, HCLK, and PCLK) and wakeup signals Figure:clock distribution of the S3C2440A. The S3C2440A has four power modes. The following section describes each power management mode. The transition between the modes is not allowed freely. Figure for available transitions among the modes. 2019/1/16 SST@BJUT

NORMAL Mode In Normal mode, all peripherals and the basic blocks including power management block, the CPU core, the bus controller, the memory controller, the interrupt controller, DMA, and the external master may operate completely. But, the clock to each peripheral, except the basic blocks, can be stopped selectively by software to reduce the power consumption. 2019/1/16 SST@BJUT

IDLE Mode In IDLE mode, the clock to the CPU core is stopped except the bus controller, the memory controller, the interrupt controller, and the power management block. To exit the IDLE mode, EINT[23:0], or RTC alarm interrupt, or the other interrupts should be activated. (EINT is not available until GPIO block is turned on). 2019/1/16 SST@BJUT

SLOW Mode (Non-PLL Mode) Power consumption can be reduced in the SLOW mode by applying a slow clock and excluding the power consumption from the PLL. The FCLK is the frequency of divide_by_n of the input clock (XTIpll or EXTCLK) without PLL. The divider ratio is determined by SLOW_VAL in the CLKSLOW control register and CLKDIVN control register. 2019/1/16 SST@BJUT

SLEEP mode The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the SLEEP mode requires two independent power sources. One of the two power sources supplies the power for the wake-up logic. The other one supplies other internal logics including CPU, and should be controlled for power on/off. In the SLEEP mode, the second power supply source for the CPU and internal logics will be turned off. The wakeup from SLEEP mode can be issued by the EINT[15:0] or by RTC alarm interrupt. 2019/1/16 SST@BJUT

Clock initialization(1) ;clock controller LOCKTIME EQU 0x4C000000 MPLLCON EQU 0x4C000004 CLKDIVN EQU 0x4C000014 ;Fin=16.9344MHz,Fout=296.35MHz M_MDIV EQU 0x61 M_PDIV EQU 0x1 M_SDIV EQU 0x2 ;to reduce PLL lock time,adjust the LOCKTIME LDR R0, =LOCKTIME LDR R1, =0xFFFFFFFF STR R1,[R0] 2019/1/16 SST@BJUT

Clock initialization(2) ;configure clock divider LDR R0,=CLKDIVN LDR R1,=0x7 STR R1,[R0] ;configure MPLL LDR R0, =MPLLCON LDR R1, =((M_MDIV<<12)+(M_FDIV<<4)+M_SDIV) STR R1, [R0] 2019/1/16 SST@BJUT

内容大纲 S3C2440A Clock & Power Management S3C2440A Watch Dog Timer 2019/1/16 SST@BJUT

2019/1/16 SST@BJUT

Features of Watchdog Timer Used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors Internal reset signal is activated for 128 PCLK cycles when the timer count value reaches 0 (time-out). used as a normal 16-bit interval timer to request interrupt service 2019/1/16 SST@BJUT

Watchdog Timer Operation 2019/1/16 SST@BJUT

几个 使用原则 Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically reloaded into the timer counter (WTCNT). In this reason, an initial value must be written to the watchdog timer count (WTCNT) register, before the watchdog timer starts The Watchdog timer is used to resume the S3C2440A restart on mal-function after its power on; if controller restart is not desired, the Watchdog timer should be disabled. If the user wants to use the normal timer provided by the Watchdog timer, enable the interrupt and disable the Watchdog timer reset. 2019/1/16 SST@BJUT

Watchdog Timer special register 2019/1/16 SST@BJUT

WATCHDOG TIMER CONTROL (WTCON) REGISTER 2019/1/16 SST@BJUT

WATCHDOG TIMER DATA (WTDAT) REGISTER 2019/1/16 SST@BJUT

WATCHDOG TIMER COUNT (WTCNT) REGISTER 2019/1/16 SST@BJUT

Disable watchdog timer WTCON EQU 0x53000000 ; ;disable watchdog timer LDR R0,=WTCON ;watchdog timer LDR R1,=0x00 STR R1,[R0] 2019/1/16 SST@BJUT

Any Questions? 2019/1/16 SST@BJUT

时钟分布 FCLK HCLK PCLK 2019/1/16 SST@BJUT