Implementation Technology Pusan National University

CMOS Basic CMOS(Complementary Metal Oxide Semiconductor) FET(Field Effect Transistor) CMOS = NMOS (N-type MOS) + pMOS (p-type MOS) MOS has three terminals, S(Source), D(Drain) and G(Gate) 2

CMOS Basic 3

CMOS Basic Poly-silicon copper SiO 2 4

CMOS Basic S G D S G D 5

CMOS Basic S D G S G D S G D S G D 6

CMOS Basic Rectangular pattern 1 Rectangular pattern 2 S G D S D G 7

CMOS Basic Question: Can we carve this 3D transistor structure on silicon substrate with those rectangular patterns? Rectangular pattern 1 Rectangular pattern 2 S D G S G D 8

CMOS Basic Fabrication basic P1 S G D P2 P2 9

CMOS Basic Fabrication basic P1 P2 S G D P2 10

CMOS Basic S D G Fabrication basic Poly-silicon copper P1 P2 Another pattern Poly-silicon copper SiO 2 11

CMOS Basic 12

CMOS Basic 13

CMOS Basic VDD VSS Output Input RT-level gate-level Layout-level module mydesign(a, b, c) … OUT = ~ IN; RT-level VDD VSS Input Output gate-level Layout-level Transistor-level (Inverter layout) 14

CMOS Basic 15

CMOS Basic 16

CMOS Basic 17

CMOS Basic 18

CMOS Basic 19

Design Process 20

Design Process 21

Design Process 22

Design Process 23

Implementation Three implementation methods Full-custom Semi-custom Semi-custom (e.g. Standard cell) FPGA(Field Programmable Gate Array) Full-custom Manual layout All fabrication steps are required for each design Semi-custom Automated layout All fabrication steps are required for each design FPGA Automated layout In fabrication steps, only personalized metallization last step is required for a specific design through the programming, and all previous fabrication steps are done beforehand, independently from the design 24

Implementation Full-custom 25

Implementation Semi-custom For layout automation, each primitive cell in the cell library must have same physical characteristic 26

Implementation Semi-custom 27

Implementation Semi-custom 28

Implementation Semi-custom 29

Implementation FPGA - Look-up table base architecture CLB Switch Matrix I/O Blocks (IOBs) Configurable Logic Blocks (CLBs) Programmable Interconnect - Look-up table base architecture - Rich flip flop application design [Source: Xilinx, Inc.] 30

Implementation FPGA CLB - Two 4-input LUTs and one 3-input LUT - Two edge-triggered FFs DIN EC SR - Four outputs Fed by “B” muxes [Source: Xilinx, Inc.] 31

Implementation FPGA - Combinational logic is stored in Look-Up Tables (LUTs) in a CLB - Example: A B C D Z 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 . . . 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Combinatorial Logic A B C D Z [Source: Xilinx, Inc.] 32

Implementation FPGA Compile Placement & routing Bit-stream generation Downloading 33

Implementation Chip vs LEGO NOR2 cell EXOR2 cell NAND2 cell Inverter cell 34

Implementation Chip vs LEGO 35

Implementation Chip vs LEGO 36

Implementation One of the most complex LEGO constructions: LEGO Venice 37

Implementation One of the most complex chips: AP for smart phones, tablet PC, etc 38

Implementation One of the most complex chips: AP for smart phones, tablet PC, etc 39