CprE 588 Embedded Computer Systems

Slides:



Advertisements
Similar presentations
SoC Challenges & Transaction Level Modeling (TLM) Dr. Eng. Amr T. Abdel-Hamid ELECT 1002 Spring 2008 System-On-a-Chip Design.
Advertisements

Presenter : Shao-Chieh Hou VLSI Design, Automation and Test, VLSI-DAT 2007.
Copyright  2003 Dan Gajski and Lukai Cai 1 Transaction Level Modeling: An Overview Daniel Gajski Lukai Cai Center for Embedded Computer Systems University.
Hardware/ Software Partitioning 2011 年 12 月 09 日 Peter Marwedel TU Dortmund, Informatik 12 Germany Graphics: © Alexandra Nolte, Gesine Marwedel, 2003 These.
ECE-777 System Level Design and Automation Hardware/Software Co-design
ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.
Combining Statistical and Symbolic Simulation Mark Oskin Fred Chong and Matthew Farrens Dept. of Computer Science University of California at Davis.
Scalable Multi-Cache Simulation Using GPUs Michael Moeng Sangyeun Cho Rami Melhem University of Pittsburgh.
Zhiguo Ge, Weng-Fai Wong, and Hock-Beng Lim Proceedings of the Design, Automation, and Test in Europe Conference, 2007 (DATE’07) April /4/17.
Constraint Systems used in Worst-Case Execution Time Analysis Andreas Ermedahl Dept. of Information Technology Uppsala University.
Enabling Efficient On-the-fly Microarchitecture Simulation Thierry Lafage September 2000.
High-Level Constructors and Estimators Majid Sarrafzadeh and Jason Cong Computer Science Department
CS244-Introduction to Embedded Systems and Ubiquitous Computing Instructor: Eli Bozorgzadeh Computer Science Department UC Irvine Winter 2010.
Behavioral Design Outline –Design Specification –Behavioral Design –Behavioral Specification –Hardware Description Languages –Behavioral Simulation –Behavioral.
Source Code Optimization and Profiling of Energy Consumption in Embedded System Simunic, T.; Benini, L.; De Micheli, G.; Hans, M.; Proceedings on The 13th.
Define Embedded Systems Small (?) Application Specific Computer Systems.
Copyright  1999 Daniel D. Gajski IP – Based Design Methodology Daniel D. Gajski University of California
1 EE249 Discussion A Method for Architecture Exploration for Heterogeneous Signal Processing Systems Sam Williams EE249 Discussion Section October 15,
EET 4250: Chapter 1 Performance Measurement, Instruction Count & CPI Acknowledgements: Some slides and lecture notes for this course adapted from Prof.
MoBIES Working group meeting, September 2001, Dearborn Ptolemy II The automotive challenge problems version 4.1 Johan Eker Edward Lee with thanks.
Transaction Level Modeling Definitions and Approximations Trevor Meyerowitz EE290A Presentation May 12, 2005.
Enhancing Embedded Processors with Specific Instruction Set Extensions for Network Applications A. Chormoviti, N. Vassiliadis, G. Theodoridis, S. Nikolaidis.
Trend towards Embedded Multiprocessors Popular Examples –Network processors (Intel, Motorola, etc.) –Graphics (NVIDIA) –Gaming (IBM, Sony, and Toshiba)
HW/SW Co-Synthesis of Dynamically Reconfigurable Embedded Systems HW/SW Partitioning and Scheduling Algorithms.
End-to-End Design of Embedded Real-Time Systems Kang G. Shin Real-Time Computing Laboratory EECS Department The University of Michigan Ann Arbor, MI
1 Embedded Computer System Laboratory RTOS Modeling in Electronic System Level Design.
(1) Introduction © Sudhakar Yalamanchili, Georgia Institute of Technology, 2006.
1 Presenter: Ming-Shiun Yang Sah, A., Balakrishnan, M., Panda, P.R. Design, Automation & Test in Europe Conference & Exhibition, DATE ‘09. A Generic.
Exploring the Tradeoffs of Configurability and Heterogeneity in Multicore Embedded Systems + Also Affiliated with NSF Center for High- Performance Reconfigurable.
Design Space Exploration
Korea Univ B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors 컴퓨터 · 전파통신공학과 최병준 1 Computer Engineering and Systems Group.
Extreme Makeover for EDA Industry
A New Method For Developing IBIS-AMI Models
Automatic Communication Refinement for System Level Design Samar Abdi, Dongwan Shin and Daniel Gajski Center for Embedded Computer Systems, UC Irvine
High Performance Embedded Computing © 2007 Elsevier Lecture 3: Design Methodologies Embedded Computing Systems Mikko Lipasti, adapted from M. Schulte Based.
High Performance Embedded Computing © 2007 Elsevier Chapter 1, part 2: Embedded Computing High Performance Embedded Computing Wayne Wolf.
Storage Allocation for Embedded Processors By Jan Sjodin & Carl von Platen Present by Xie Lei ( PLS Lab)
Hybrid Prototyping of MPSoCs Samar Abdi Electrical and Computer Engineering Concordia University Montreal, Canada
Macro instruction synthesis for embedded processors Pinhong Chen Yunjian Jiang (william) - CS252 project presentation.
A Methodology for Architecture Exploration of heterogeneous Signal Processing Systems Paul Lieverse, Pieter van der Wolf, Ed Deprettere, Kees Vissers.
CprE / ComS 583 Reconfigurable Computing
Fast Simulation Techniques for Design Space Exploration Daniel Knorreck, Ludovic Apvrille, Renaud Pacalet
A Graph Based Algorithm for Data Path Optimization in Custom Processors J. Trajkovic, M. Reshadi, B. Gorjiara, D. Gajski Center for Embedded Computer Systems.
A Single-Pass Cache Simulation Methodology for Two-level Unified Caches + Also affiliated with NSF Center for High-Performance Reconfigurable Computing.
Design & Co-design of Embedded Systems Next Step: Transaction-Level Modeling Maziar Goudarzi.
CS244-Introduction to Embedded Systems and Ubiquitous Computing Instructor: Eli Bozorgzadeh Computer Science Department UC Irvine Winter 2010.
MILAN: Technical Overview October 2, 2002 Akos Ledeczi MILAN Workshop Institute for Software Integrated.
Active Sampling for Accelerated Learning of Performance Models Piyush Shivam, Shivnath Babu, Jeff Chase Duke University.
Presentation by Tom Hummel OverSoC: A Framework for the Exploration of RTOS for RSoC Platforms.
CprE 588 Embedded Computer Systems Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #5 – System-Level.
An Integrated Design Environment to Evaluate Power/Performance Tradeoffs for Sensor Network Applications Amol Bakshi, Jingzhao Ou, and Viktor K. Prasanna.
Teaching The Principles Of System Design, Platform Development and Hardware Acceleration Tim Kranich
An Automated Development Framework for a RISC Processor with Reconfigurable Instruction Set Extensions Nikolaos Vassiliadis, George Theodoridis and Spiridon.
Physically Aware HW/SW Partitioning for Reconfigurable Architectures with Partial Dynamic Reconfiguration Sudarshan Banarjee, Elaheh Bozorgzadeh, Nikil.
1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture.
Lecture 1: Introduction CprE 585 Advanced Computer Architecture, Fall 2004 Zhao Zhang.
1 COMP427 Embedded Systems Lecture 3. Virtual Platform Prof. Taeweon Suh Computer Science Education Korea University.
Embedded Real-Time Systems
System-on-Chip Design
Andreas Hoffmann Andreas Ropers Tim Kogel Stefan Pees Prof
Chapter 1: Introduction
IP – Based Design Methodology
Gabor Madl Ph.D. Candidate, UC Irvine Advisor: Nikil Dutt
An Embedded Systems Course and Course
Estimating Timing Profiles for Simulation of Embedded Systems
Suhas Chakravarty, Zhuoran Zhao, Andreas Gerstlauer
HIGH LEVEL SYNTHESIS.
CprE 588 Embedded Computer Systems
Department of Electrical Engineering Joint work with Jiong Luo
Transaction Level Modeling: An Overview
Presentation transcript:

CprE 588 Embedded Computer Systems Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #8 – Architectural Specialization

CprE 588 – Embedded Computer Systems Outline Motivation Related Work Design Flow Basic Concepts Multi-Metrics Experimental Results Conclusion L. Cai, A. Gerstlauer, and D. Gajski, “Retargetable Profiling for Rapid, Early System-Level Design Space Exploration”, In Proceedings of the Design Automation Conference (DAC), 2004. CprE 588 – Embedded Computer Systems Mar 3-5, 2009

Higher levels of abstraction Motivation Time-to-market  SoC Complexity  Higher levels of abstraction Exploration Estimation Modeling level n Verification Refinement n+1 Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

System Level Estimation Fast Accurate  Fidelity Different abstraction levels Wide range of metrics Wide variety of target implementation Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Related Work Static analysis-based approaches Examples WCET (Y. Li), scheduling analysis (G. Buttazzo) Memory size estimation (Y. Zhao) Limitations Time-consuming, manual interference Dynamic simulation-based approaches Profiling tools (GNU profiler) Instruction-set simulators Multi-processor, multi-level co-simulation (P. Gerin) Trace-based simulation (K. Lahir, P. Lieverse) A simulation is required for each design alternative Target/host machine-dependent characteristics Operation-related data Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Design Flow Refinement Estimation GUI Spec Simulation model Profiling Profiling Spec characteristics Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Design Flow (cont.) Refinement Estimation GUI Spec Simulation model Profiling Profiling Spec characteristics Design decision Retargeting Refining Retargeting Back Implt annotation Characteristics Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Design Flow (cont.) Refinement Estimation GUI Spec Instru- model menting Profiling Profiling Spec characteristics Design decision Retargeting Refining Retargeting Back Implt annotation Characteristics Refined Simulation/ Implt. Simulation- estimation model estimation Estimates Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Explore and Trim Exploration Space Profiling Implt independent simulation One-time retargeting Implt dependent simulation ... /estimation ... Design Time Profiling Retargeting Simulation- stage stage estimation stage Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Profiling Instrumentation-based profiling Bb: The execution counts of basic block b Cb,i,d: No. of computed characteristics for item type i and data type d in the block b Data type i: float, int, .. Item type d: metric dependant Ri,d = bC b,i,d Bb R = idRi,d int b,c; if( a = 0){ b++; } else{ c++; B1 = 1 C1,++,int = 1 B3 = 3 C3,++,int = 2 R++,int=  i [ Bi * Ci,++,int ] =1 x 1 + 3 x 2 = 7 Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Retargeting Impl. characteristics Ri,d: Spec. characteristics Wi,d : weights of components which the entity mapped to Manual Simulation E = id(Ri,d X Wi,d ) Time complexity: O(n) v c B1 B2 B R(B1)++,int= 7 W(PE1)++,int= 1 PE1 PE2 Mem E(B1,PE1)++,int= 7 x 1 = 7 CprE 588 – Embedded Computer Systems Mar 3-5, 2009

CprE 588 – Embedded Computer Systems Challenges Separating dynamic and static analysis Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Challenges (cont.) Separating dynamic and static analysis Supporting complex models Hierarchy Recursion v c B1 B2 B Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Challenges (cont.) Separating dynamic and static analysis Supporting complex models Hierarchy Recursion Multi-dimensional analysis v c B1 B2 B Traditional approach Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Challenges (cont.) Separating dynamic and static analysis Supporting complex models Hierarchy Recursion Multi-dimensional analysis Multi-entities Behavior, channel, port, variable v c B1 B2 B Entities Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Challenges (cont.) Separating dynamic and static analysis Supporting complex models Hierarchy Recursion Multi-dimensional analysis Multi-entities Behavior, channel, port, variable Multi-metrics Operation, traffic, storage Static, dynamic v c B1 B2 B Entities Metrics CprE 588 – Embedded Computer Systems Mar 3-5, 2009

CprE 588 – Embedded Computer Systems Challenges (cont.) Separating dynamic and static analysis Supporting complex models Hierarchy Recursion Multi-dimensional analysis Multi-entities Behavior, channel, port, variable Multi-metrics Operation, traffic, storage Static, dynamic Multi-levels Application, transaction, bus-functional v c B1 B2 B Entities Levels Metrics CprE 588 – Embedded Computer Systems Mar 3-5, 2009

CprE 588 – Embedded Computer Systems Operation Metrics Entities: behavior Item types 84 basic types: ‘+’.., ‘=‘.., ‘if’.. Special operation types: global function Specification characteristics Mapping: behavior  PE Implementation characteristics Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Traffic Metrics Entities: port, variable, channel, behavior Item types: in, out Specification characteristics Mapping: Port  PE Variable/channel  bus Implementation characteristics Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

Deriving Traffic Metrics Profiling for the hierarchically instantiated behaviors and recursively called functions A.p1  B.p2  B.F1.p3  B.F2.P4 Different abstraction levels PE1 PE2 Beh1 Beh2 PE1 PE2 v1 Beh.port → Var Beh.port → Chan Chan in Chan Beh.port → Pin Chan.port  Chan CprE 588 – Embedded Computer Systems Mar 3-5, 2009

CprE 588 – Embedded Computer Systems Storage Metrics Entity: variable, behavior Item types: local, global Specification characteristics Mapping: Variable  local/global memory Implementation characteristics Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

Exp. Result: Vocoder Profiling Floating –point not required Dedicated hardware multipliers HW acceleration Table 1: Computational complexity of top-level Vocoder behaviors Table 2: Codebook operation mix Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

Exp. Result: Vocoder Profiling (cont.) 1500 2500 3500 4500 10 30 50 70 90 110 130 150 170 u Timing constraint (2990) Time (ms) Cost B (73, 2980) 8 behaviors  3 PEs Total 38 =6561 design alternatives Evaluation time: 3:15 hour 1 simulation (2.23s) 1 profiling (8.41s) 6561 retargeting (0.8s) 6561mapping (0.97s) yellows Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

Exp. Result: JPEG Encoder Implementation characteristics vs implementation estimates 50 100 150 200 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Design alternatives Execution time (ms)) Estimates Char. Map 4 behaviors  2 PEs: 24 design alternatives Accuracy: 12.5%, fidelity = 100% Mar 3-5, 2009 CprE 588 – Embedded Computer Systems

CprE 588 – Embedded Computer Systems Conclusion Dynamic profiling + static retargeting Profiling: helps completely comprehend the specification Retargeting: ultra-fast (linear time), enables initial, exhaustive exploration of design space. Multi-dimensional analysis Multi-entities Behavior, channel, variable, port Multi-abstraction levels Application level, transaction level, bus-functional level Multi-metrics Operation, traffic, storage Static, dynamic Mar 3-5, 2009 CprE 588 – Embedded Computer Systems