Introduction to Digital System and Microprocessor Design Week 5, Appendix Introduction to Digital System and Microprocessor Design Wonju Seo, Daehyun Ahn tjdnjswn22@postech.ac.kr Mar 21, 2017 Slides made by Sungju Ryu, DICE 1/24

Verilog Syntax 2/24

Verilog Language One of the most popular HDL. It’s syntax is similar with C. Statement should end with ; Commenting is same: /* */ and // using C’s basic operators such as &, ^, >>. Timing is very important. 3/24

Two method to write your code Gate Level Programming with only gates. (+) Mostly, synthesizable, which means it can be H/W, if you pass simulation. (-) Hard to make complicated H/W. RTL (Register Transfer Level) Design your source code using abstraction, which models circuits as a flow of data signals between registers and logical operation(ex. &, |). (+) Compiler do translation RTL to Gate Level. (-) sometimes, hard to be a real H/W register: storage that synchronized with clock 4/24

Verilog programming is different with Standard C programming. Reminder Verilog programming is different with Standard C programming. 5/24

Difference between C and Verilog Purpose Software Hardware description Line Ordering Important Not Important Paragraph separators { } If/endif Endmodule …. Datatype Int/char … wire/register … Execution Line by line concurrently 6/24

Verilog Code Structure /* example.v*/ /* Macros */ module digitalDesign (/*input and output ports*/) /* Data Declaration*/ wire [3:0] CiTE; reg [4:0] student_number; /* Link other modules& assign wires */ assign CiTE = student_number[3:0]; /* Behavior Declaration */ endmodule 7/24

Module Module is an abstractions for your Logic. You need to specify “top file” which have top module. Your Design goes clear and easier if you use module properly. As a abstraction point of view, its scheme is very similar with C’s function; however, the contents of a module work simultaneously. Declaration: Module MODULE_NAME () /* Module content */ endmodule 8/24

Module Usage: case by case Suppose there are module A B C, and we set A is a top module. Installation MODULE_NAME identifier(); Multiple use of a Module Possible, just give different identifier. Not used module like C not Include in the H/W B can install module C inside. A’s content and B’s content work at same time. Module A () /* Module content */ Wire a; B b1(); B b2(); Assign a = 1 | 0; */ endmodule 9/24

Data types The method for dealing with the digital data in Verilog. There are two basic types: Register/Nets Register => For sequential logic most common type is “reg” the place where data is stored and hold their value before change. Give value in always/initial block. Can be used for latch/flip flops. It does not mean physical register; think it as variable that store value in C. Nets => For combinational logic most common type is “wire” virtual wire that will be physical wire between registers. Not hold value; it just use register’s value. Assign means connect nets with register, gate’s output, or real value. 10/24

Wire case Value of A == value that register hold Register Wire A Value of D == the gate’s output Wire B Gate Wire D Wire C VDD Value of E == always 1 Wire E GND Value of F == always 0 Wire F 11/24

Declaration & Assignment Data_type {[length]} Indetifier; {} is optional Most of design can be done with reg and wire. Identifier must start with alphabetic character, and should not be keyword like reg, or wire. Example reg [0:7] A; // Declare A as a register which length is 8, and MSB is 0th bit. reg [7:0] B; // Declare B as a register which length is 8, and MSB is 8th bit wire [3:0] C; // Declare C as a wire which length is 4, and MSB is 4th bit. wire D; // Declare D as a 1 bit wire. wire E, F;// Declare two wire named E, F. 12/24

Data Representation How Verilog represent digital Value. Basic four type: X(undefined), Z(High Impedance), 0, 1 Binary and hex number is natural and is preferred for debugging, but you can use other number system. You need to specify the number of bit and the number system using h, b, or o. number of bit should be larger than the least bit, more is fine. Decimal Least bit Binary Hexadecimal 5 3 3’b101 4’h5 32 6 6’b100000 6’h20 7 3’b111 3’h7 13 4 4’b1101 3’h13 (Wrong) Z 4’bzzzz 4’hz 13/24

Data Assignment for wire types. The way wire type connected is assignment. You need to use “assign” keyword inside the module to do this. Before assignment, you need to declare first. If the number of bits for value exceed the length of wire, then higher bits are ignored. wire [4:0] A;// Declare 5 bits wire A Wire B,C ; // Declare 1 bit wire B, C Wire [4:0] D; // Declare 5 bit wire D assign A = 5’h19; // set wire to be 19. assign B = 5’h19; // B will be 1. assign C = A; // C will indicate A’s lowest bit or compiler error. Assign D = {B, C, A[2:1], A[4] 1}; // Assign D as B:C:A[2:1]:A[4]:1 (concatenation) 14/24

Operators The method to deal with operations in Verilog You can assign the result of operations to wire. Ex) assign A = 3 | 5; or assign D = C & B; Operators are similar with C. Arithmetic: +, -, *, /, !, ~ Binary operator: &, |, ^, ~, ! Shift: <<, >> (logical), <<<<, >>> (Arithmetic) Logical: &&, ||, !, >, <, <=, >=, ==, !=, ===, !== (checking for Z, X, mostly non-syn) 15/24

Module: I/O Port Port is a communication method within modules. Three types of port: input, output, and inout. Input Port: it will be input, it should not be register. Output Port: it will be output, it can be register or wire. Inout port: it will be used as in/out. If you want to use port, you need to specify its type like other variables. Default port is wire. Of course, You cannot Change the value of input port; you can only change the value of outputs. Module ANDGATE (output wire[1:0] o, input wire[1:0] A, input wire[1:0] B); Assign o = A & B: endmodule 16/24

Communication Between modules You can use other modules inside module if other module is predefined. If you do not specify the port, the given order will be connected to each port. If you want to specify the port, the corresponding port will be connected. To do this, use “.PORT_NAME(CONNECTION_NAME)” see below. For below example, suppose module ANDGATE is predefined, and o is output, A and B is input. Module twobit_AND (output wire [1:0] o, input wire [1:0] A, input wire [1:0] B) ANDGATE and1(o[0], A[0], B[0]); ANDGATE and2(.o(o[1]), .A(A[1]), .B(B[1])); endmodule 17/24

Difference between C - Module Module looks like function in C. However they are different; in Verilog, if you define module, it is virtually defined and you can use as much as you want. Install a module is not a jump to that module. It means make new copy of it. A’s copy 1 Module A (Declaration) A a1(); A a2(); A a3(); A’s copy 2 A’s copy 3 18/24

Macro/Comment Macro is for programming efficiency or readability of your code. Later matched strings will be replaced into string that you defined. Comment is a additional information, which is not part of your H/W; it just gives more information for later readers, or even you. Two method are possible using // and /* */ like C //: comment after this before line changed /* */: comment inside of /* */ `define MAXIMUM 500 // define MAXIMUM Module A() wire maximum = MAXIMUM; /* this will be replaced into wire a = 500*/ endmodule MAXIMUM is replaced into 500 Maximum is not replaced into 500. Line 2 and line 6~7 are comment. 19/24

Delay You cannot use delay in real H/W. (think, how can you implement using Gates) But for testing your logic, exact timing information might be needed. For Above reason, Verilog support delay for testing only. Do not use below in the logic! Your H/W will not work. Even for simulating your logic. Usage: # delay_time; 20/24

Testbench Testbench is a Verilog file(.v) for simulating the behavior of code. It doesn’t have to be synthesizable, which means you can use any “Verilog syntax” to test your program. Testbench example. Best example is last day classes testbench. 21/24

Example of test bench. Now you should understand left code. Always block and reg will be touched later. At this time, just think like this, reg: variable in C always: inside of it, its content works repeatedly until end. 22/24

Testbench vs Normal File Normal Verilog extension .v Syntax Checking Yes yes Synthesizability No Freedom Much Little Purpose Test Verilog files Implementation 23/24

Reminder. All statements are executed concurrently, even some are in other modules. Below results should be same. Suppose initially, A is 0, B is 0, and C is 1 A = B & C; B = C | 1; B = C | 1 A = B & C 24/24